DE Module 5: VHDL Introduction

DE Module 5: VHDL Introduction

• VHDL (Very High Speed Integrated Circuits Hardware Description Language) is a hardware description language used to describe hardware.
• Verilog is another popular hardware description language that is based on the C language.
• VHDL was developed by the U.S. Department of Defence.
• VHDL follows IEEE Standard 1076-1987, 1993 and 200x
• Verilog has an IEEE Standard 1364-1995, 2001 and 2005

Contents

• Different design styles are part of the module.
• Implementation of adder, subtractor, multiplexer and flip-flop are covered.

Introduction

• Hardware Description Languages (HDL) are used to describe hardware.
• VHDL and Verilog are two popular HDLs.

Applications of HDL

• Modeling and documenting digital systems using different abstraction levels (behavioral, structural, etc.).
• Verifying design circuits.
• Converting designs from higher abstraction levels to lower abstraction levels.

Features of VHDL

• Describes, models and verifies a system before synthesis.
• Allows description of concurrent systems.
• Is multipurpose.
• Supports flexible design methodologies (top-down, bottom-up or both).
• Supports various modelling types (behavioral or sequential, dataflow, structural).
• Makes large-scale design easier with components, functions, procedures, packages and configuration.
• Allows test benches to be written in the same language as the circuits.
• Allows circuits to be verified before synthesis.

Structure of VHDL Code

• VHDL code structure has four key parts:
  • Library Declaration
  • Entity
  • Architecture
  • Configuration

Library Declaration

• To make a package visible in the design, two declarations are required:

  • Library Clause
  • Use Clause

• A design typically needs libraries from at least three different libraries: (e.g., ieee, std, work).

Entity

• Describes the external view of the device.

• Includes at least one architecture associated with it.

• Declares the name and list of interface ports.

• Ports represent signals used for communication with other devices or terminals.

• Input and output ports are specified within the entity.

Entity Syntax

• The basic structure of an entity definition:
  • ENTITY entity_name IS
    • Port(
      • Port_name : signal_mode signal_type;
      • Port_name : signal_mode signal_type )
    • END entity_name;

Rules to write entity name

• The first letter of the entity name must be an alphabet.
• Special characters are allowed only as underscores.
• Two consecutive underscores aren't allowed.
• The entity name cannot end with a special character.

Signal Modes

• Describes how a signal is used (input, output, inout, buffer) within the design.
• For example, counter state, shift register state.

Signal Types

• Commonly used signal types:
  • bit
  • bit_vector
  • std_logic
  • std_logic_vector

Entity Declaration of a Circuit

• Example of entity declaration for a circuit with inputs A, B, S and outputs X, Y:

  • entity my_ckt is
    • port (
      • A: in bit;
      • B: in bit;
      • S: in bit;
      • X: out bit;
      • Y: out bit);
  • end my_ckt;

Write entity declaration for NOR gate

• entity nor_gate is       port (A, B: in STD_LOGIC;                 Y: out STD_LOGIC); end nor_gate;

Architecture Body

• A VHDL architecture defines how the hardware entity's behavior is implemented.
• There are three ways to implement this architecture: dataflow, behavioral, and structural.

Syntax of Architecture

• The syntax of an architecture body includes a declarative part and a statement part.

VHDL Operators

• Several types of operators are used in VHDL (assignment, logical, relational, shift, adding, multiplying and miscellaneous).

Assignment Operators

• Used to assign values to signals, variables, and constants.
• The assignment operator <= is used to assign a value to a Signal and the assignment operator := for variable, constant or Generic.

Logical Operators

• The seven logical operators use bit operands and produce bit results.
• Examples include AND, OR, NAND, NOR, XOR, XNOR, NOT.

Relational Operators

• VHDL supports equality and inequality operators.
• Operators include: =, /=, <, <=, >, >=;

Shift Operators

• Examples include Shift left logical, Shift right logical, Shift left arithmetic, Shift right arithmetic, Rotate Left, Rotate Right.

Adding Operators

• Includes addition, subtraction, and concatenation.
• Example a & b where & is used for concatenation.

Multiplying Operators

• Includes multiplication, division, Mod (modulus operator), Remainer.

Miscellaneous Operators

• Functions include Absolute, Exponentiation, Negation.

Data Flow Style

• Example VHDL code for a NOR gate in data flow style, which describes how the hardware functions.

Write VHDL Code for Half adder

• Example of Half adder code in data flow style .

Behavioral Style (Sequential Execution)

• This describes the behavior of the hardware through a series of sequential steps like if-then-else, and elsif statements.

VHDL Code for Half Adder in Behavioural Style

• VHDL code for half adder design using if-then-else statements (a behavioural approach).

Problems

• This module describes how to implement a 4-1 multiplexer in behavioural style using if-then-else statements.

Attributes

• Attributes are used to increase the flexibility of code.
• Useful for handling different data types/ sizes for code.
• Important attributes: Clk'EVENT, RISING_EDGE(clk)

D Flip-Flop

• VHDL code structure for D flip flop.

JK FF using variable

• VHDL code structure for JK flip flop that uses variable for logic implementation.

SR FF using variable

• VHDL design using variables for SR Flip-flop logic.

T FF using variable

• VHDL design using variables for T Flip-flop logic.