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IN3160, IN4160 Digital system design Introduction HDL, PL and Design flow Yngve Hafting Overview – General information – Intro to programmable Logic Course management What is programmable logic? Schedule Why choo...

IN3160, IN4160 Digital system design Introduction HDL, PL and Design flow Yngve Hafting Overview – General information – Intro to programmable Logic Course management What is programmable logic? Schedule Why choose programmable logic? Course Goals Curriculum – Design Flow for digital designs Lab assignments Who are we – Intro to our hardware…: Zedboard – Motivation – Architecture Why Digital Design? – Documentation Why HDL? «Our» HDL: VHDL - Assignments and suggested reading for this week Course Management Lecturers: – Alexander Wold (II’er) – Yngve Hafting (Universitetslektor) Lab supervisors / teachers: – Elias Ringkjøb (student) – Jonas Wenberg (student) – Øystein Øverbø (student) Lectures Tuesday 10:15 -12:00, OJD Caml Friday 10:15-12:00, OJD Caml Lab LISP (2428): TBD- lab will be manned certain time slots- poll next slide https://www.mn.uio.no/ifi/om/finn-fram/apningstider/ Tid Monday Tuesday Wednesday Thursday Friday (.15) 8 10 Lecture 10-12 Lecture 10- 12 12 IN3050 Lecture 14 Øystein Elias Jonas 16 Web http://www.uio.no/studier/emner/matnat/ifi/IN3160/ (covers also INF4160) Where do we stand + lab supervision poll? www.menti.com Code 2536 2149 (ROBIN) Study program connections IN5200 Advanced Digital System Design Courses in electronics and circuit theory, such as Master FYS1210 - Electronics IN3160/IN4160 FYS3220 - Linear circuit theory Bachelor Digital System Design FYS3240 - Data acquisition and control provide a complementary background IN2060 that may help understanding digital Digital Design and systems in general. Computer Architecture IN1020 Introduction to FYS4220 - Real time and Embedded computer technology Data Systems overlaps with 6p Relevancy Intelligent systems Robotics SoC Asic Design Design Finishing this FPGA Design course you will Digital Software be able to do Design Analog electronics work within the electronics field of digital IN3160/IN4160 Digital System Design design. Course Goals and Learning Outcome https://www.uio.no/studier/emner/matnat/ifi/IN3160/index-eng.html In this course you will learn about the design of advanced digital systems. This includes programmable logic circuits, a hardware design language and system-on- chip design (processor, memory and logic on a chip). Lab assignments provide practical experience in how real design can be made. After completion of the course you'll:...... IN3160 vs IN4160... IN3160 IN4160 After completion of the course you'll: After completion of the course you'll: – understand important principles for design and – understand important principles for design and testing of digital systems testing of digital systems – understand the relationship between behavior and – understand the relationship between behavior and different construction criteria different construction criteria – be able to describe advanced digital systems at – be able to describe advanced digital systems at different levels of detail different levels of detail – be able to perform simulation and synthesis of digital – be able to perform advanced simulation and systems. synthesis of digital systems – be able to perform advanced implementation and analysis techniques NOTE: these are MINIMUM requirements for passing an exam. You will be given the same opportunities to learn, and the curriculum is the same. Grading will be (slightly) stricter for IN4160 due to added minimum requirements Otherwise, this course will be held as one. Our approach (compared to other studies) Focus on relevancy for students with programming skills – less physics and maths oriented less transistor and PCB technology less focus on mathematical proofs and methods less focus on tweaking (IN2060 covered this) Focus on design strategies – High level code (New -24: Testbenches in python) – Schematics / Diagrams – Verifiability – State machines Focus on physical realization on FPGA – Full tool chain used in industry  Syllabus Dally, William J. - Harting, R. Curtis - Aamodt, Tor M. Digital Design Using VHDL A Systems Approach Cambridge University Press 2016 ISBN9781107098862 Lectures and lecture slides Mandatory assignments Handouts – Will be made available digitally on semester page (Link from 2022 can be used until the 2023 link is ready) – Cookbook – Articles (Reset Circuits, Steve Kilts)  Lab assignments There are 10 obligatory lab assignments. – The book has chapter-exercises that can be used for self-study. All assignments must be completed to take the exam. – Lab workload and complexity increases through the semester Lectures are prerequisite for some assignments – Lectures most intensive in the beginning The lab assignments utilises the digilent Zedboard, featuring a Xilinx Zynq 7020 device that includes both a hardcoded ARM processor and FPGA fabric. You will be introduced to tools and board first. https://store.digilentinc.com/zedboard-zynq-7000-arm-fpga-soc-development-board/ By the end of this course you will design a system, using both processor and FPGA fabric, that will both regulate, read and display the speed of an electric motor connected to the board.  LAB Lab starts now! – Assignments are available in Canvas! – Assignments are individual. WHAT ABOUT... – Collaboration? – Previously approved assignments? – ChatGPT? – There will be one assignment (3) using peer review only. Your reviews are mandatory for your approval! – Some assignments may require that you show your setup to the lab supervisor. Labs can be done entirely remote, but on-site is strongly adviced. LISP (2428) is the LAB. – Both hardware and software will be available in LISP. 4 boards with camera will be available online for those in quarantine/ isolation / specieal needs. Questions..?  Software Vivado, Vitis – Floorplanning and Programming FPGA boards – https://www.xilinx.com/products/design-tools/vivado.html Standard edition is free and should be sufficient up to assignment 9. Tool chain for Python Testbenches = Vivado + these https://robin.wiki.ifi.uio.no/Cookbook (Not complete, but has installation guide) – GHDL Open source VHDL simulation, used together with CocoTB below. – GTKWave Open source waveform viewer – CocoTB Cosimulation framework for Python testbenches This is invoked when using "make" when using python based testbenches. Questa=Modelsim (Fallback solution if GHDL fails) – Compilation, Simulation, waveform viewer – "industry standard" – Not open source. Access may be limited All software can be accessed from Linux machines on IFI, and IFI- digital-electronics GHDL+ GTKWave and Cocotb Resources Semester page/ course web "Vortex" – Course information Exam date, lecture schedule, etc. Canvas (link from semester page) – Assignment-files, delivery and -feedback – Some links to external content in3160-discourse – Communication and discussion: Requires login, allowes anonymous posting. Both students and staff can answer ☺ – Note: Use the manned lab hours as much as possible for questions. https://robin.wiki.ifi.uio.no/Cookbook HDL & PL Hardware Description Language & Programmable Logic Yngve Hafting Overview How to implement digital designs? HDL vs schematics Why use HDL... HDL vs Software Hardware – ASICs vs PL – Some types of PL  How to implement digital designs..? Low Level – Netlists – Schematic diagrams – Programming using hardware description languages (HDL programming) IN3160... High Level – HDL programming (RTL) – Block diagrams Connecting premade models (IP's) – High level synthesis... Code Generators (Matlab/Simulink) – Uses IP's – Generates HDL/ Netlists  HDL vs netlists/ Schematics Syntesis enables – One design Several physical implementations 19 Why HDL? Technology independent code Different abstraction layers Netlist: Boolean equations: U1: xor2 port map(a(0), b(0), x(0)); aeqb numeric_std port ( clk, reset : in std_logic; Entity a,b,c : in std_logic_vector(N-1 downto 0); vdata : in std_logic; – Port size uses generic tvalid : out std_logic; tdata : out std_logic_vector(N*2 downto 0) ); end entity pipelined; Signals architecture RTL of pipelined is – Register input (next_) signal next_ab,r_ab : signed(N downto 0); signal next_c, r_c : signed(N-1 downto 0); – Registers that are not signal next_tdata : std_logic_vector(N*2 downto 0); entity outputs signal r_vdata : std_logic; – Check sizes... Should match diagram! 8  begin REGISTER_ASSIGNMENT: process(clk) is begin Architecture++ if rising_edge(clk) then if reset then r_ab '0'); r_c '0'); Registers tdata '0'); r_vdata