CENG328_LN04 - Copy.pdf

Lecture 04: The Atmel ATmega328P 𝛍𝐂 Dr. Abdulmalik Alwarafy Spring 2024 CENG 328: Introduction to Embedded Systems Outline Atmel ATmega328P AVR CPU AVR CPU Instructions Memory Memory Model Addressing Modes Contents of this lecture map to CLO 2 Introduction to Embedded Systems 3 Recall: 8-bit Atmel A...

Lecture 04: The Atmel ATmega328P 𝛍𝐂 Dr. Abdulmalik Alwarafy Spring 2024 CENG 328: Introduction to Embedded Systems Outline Atmel ATmega328P AVR CPU AVR CPU Instructions Memory Memory Model Addressing Modes Contents of this lecture map to CLO 2 Introduction to Embedded Systems 3 Recall: 8-bit Atmel ATmega328/P microcontroller ARDUINO UNO R3 Board https://en.wikipedia.org/wiki/ATmega328 The Atmel AVR Microcontroller The 8-bit Atmel AVR was introduced in 1996 The AVR adopts a modified Harvard architecture, with program & data stored in separate physical memory address space, but has the ability to read data items from program memory, using special instructions The AVR family of microcontrollers is divided into four subgroups: Tiny AVR Mega AVR XMega AVR Application-specific AVR Introduction to Embedded Systems 6 Atmel ATmega328P Microcontroller ATmega328P in 28-pin A low-power CMOS 8-bit microcontroller Based on AVR enhanced Reduced Instruction Set Computing (RISC) architecture Single cycle execution 32 general purpose registers 28/32 pins CMOS: Complementary Metal-Oxide-Semiconductor Introduction to Embedded Systems ATmega328P in 32-pin 7 RISC vs CISC Introduction to Embedded Systems 9 Little-endian vs Big-endian Little-endian: The least significant byte of data is placed at byte with lowest address. Big-endian: The most significant byte of data is placed at byte with lowest address. Little-Endian Big-Endian Different ATMega328 Packages Micro Leadframe or Quad-flat no-leads (MLF/VQFN) Quad-flat Package (TQFP) Dual in-line Package (DIP) Check https://www.ti.com/support-packaging/find-packages.html for examples of IC packaging Introduction to Embedded Systems 11 Different ATMega328 Packages..cont Dual in-line package (DIP) Quad-flat Package (TQFP) Pin Descriptions (Atmel ATmega328/P pages 17-20) Introduction to Embedded Systems 12 Atmel ATmega328P Introduction to Embedded Systems 13 AVR CPU Core 14 Introduction to Embedded Systems AVR CPU Core ALU Registers: 32 (R0-R31), 8-bit general purpose working registers Directly connected to ALU Instructions can use any register 8-bit Status Register (SREG) Program Counter (PC) Instruction Register Instruction Decoder Stack Pointer (SP) 15 ALU The high-performance AVR ALU operates in direct connection with all 32 general purpose registers Within single clock cycle, arithmetic operations between registers or between a register & an immediate are executed. ALU operations are divided into three main categories: Arithmetic, logical & Bit-functions Some implementations of ALU also provide a powerful multiplier supporting both signed/unsigned multiplication & fractional format Introduction to Embedded Systems 16 The AVR CPU Registers The AVR CPU has a register file of thirty-two 8-bit general-purpose registers with single clock cycle access time. This allows singlecycle ALU operation In a typical ALU cycle, the operation is performed on two register operands, & result is stored back in register file Six of the 32 registers can form 16-bit address pointers (referred to as X, Y, & Z pointers) for addressing data memory The Z register can also be used as an address pointer to read from and/ or write to the flash program memory, signature rows, fuses, and lock bits. Each CPU register of the Mega AVR devices is assigned a data memory address pointer registers Status Register (SREG) The SREG contains information about the result of the most recently executed arithmetic instruction The information can be used for altering program flow in order to perform conditional operations The SREG is updated after all ALU operations 18 Status Register (SREG) …Cont Bit 7 – (I): Global Interrupt Enable This flag is the global interrupt enable flag & must be set to 1 to enable interrupts If this flag is cleared to 0, all interrupt sources are disabled This flag is set & cleared by the application using SEI (set global interrupt flag) & CLI (clear global interrupt flag) instructions Status Register (Atmel ATmega328/P book page 27) AVR Stack Pointer (SP) Address The Stack is a portion of memory used for: 7FFFFFFC 7FFFFFF8 ❑ storing temporary data, 7FFFFFF4 7FFFFFF0 ❑ storing local variables, ❑ storing return addresses after interrupts & subroutine calls The Stack grows from higher to lower memory locations The SP points to the data SRAM Stack area where the interrupts & subroutine Stacks are located Data 12345678 $sp Address Data 7FFFFFFC 12345678 7FFFFFF8 AABBCCDD 7FFFFFF4 11223344 $sp 7FFFFFF0 last-in-first-out queue SP Register always points to top of Stack SP is implemented as two 8-bit registers 20 AVR Stack Pointer (SP) Exercise: Show the SP for the following memory addressing when adding new data SP SP Extra resources: The Stack: Last in, First out: https://www.youtube.com/watch?v=IWQ74f2ot7E The Stack in a Microprocessor: https://www.youtube.com/watch?v=d-2Peb3pCBg&t=384s Introduction to Embedded Systems 21