Buses PDF

Buses Computer Components: Top Level View Computer Modules  Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals – Read – Write – Timing Input/Output Connection(1) Similar to memory from computer’s viewpoint Output – Re...

Buses Computer Components: Top Level View Computer Modules  Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals – Read – Write – Timing Input/Output Connection(1) Similar to memory from computer’s viewpoint Output – Receive data from computer – Send data to peripheral Input – Receive data from peripheral – Send data to computer  CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts  What is a Bus? A communication pathway connecting two or more devices Usually broadcast (all components see signal) Often grouped – A number of channels in one bus – e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown Basic Architecture: Personal Computer Memor VESA y bus PCI EISA ISA Bus USB  Basic Architecture: Bus Standards ISA (Industry Standard Architecture): 8 MHz 8-bit (8086/8088) 16-bit (80286-Pentium) EISA: 8 MHz 32-bit (older 386 and 486 machines). PCI (Peripheral Component Interconnect): 33 MHz 32-bit or 64-bit (Pentiums) New: PCI Express and PCI-X 533 MTS VESA (Video Electronic Standards Association): Runs at processor speed. 32-bit or 64-bit (Pentiums) Only disk and video. Competes with the PCI but is not popular  Basic Architecture: Bus Standard (cont.) USB (Universal Serial Bus): 1.5 Mbps,12 Mbps, 480 Mbps and now 5Gbps. Newest systems. Serial connection to microprocessor. For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. AGP (Advanced Graphics Port): 66MHz Newest systems. Fast parallel connection: Across 64-bits for 533MB/sec. For video cards. To accommodate the new DVD (Digital Versatile Disk) players. Latest AGP 3.0 with peak bandwidth of 2.1GB/s.  Data Bus Carries data – Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance – 8, 16, 32, 64 bit Terminology  Data Little-endianRepresentations byte ordering in memory  Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system – e.g. 8080 has 16 bit address bus giving 64k address space  Memory Addressing Mode Flat-addressing – a single, continuous linear address space of 232 bytes Segmented-addressing – a logical address consisting of a segment selector and an offset – Exe. 8086 have 16 segments of 64K 16  Memory addressing – Flat- mode A flat mode memory system is one in which there is no segmentation. – does not use a segment register to address a location in the memory First byte address is at 00 0000 0000H; the last location is at FF FFFF FFFFH. – Example of address of 40-bits The flat mode memory contains 1T byte of memory using a 40-bit address. In the future, Intel plans to increase the address width to 52 bits to access 4P bytes of memory. The flat mode is only available in the Pentium 4 and Core2 that have their 64- bit extensions enabled. Memory Addressing - Segmented Mode All real address mode must consist of a segment address plus an offset address. – segment address - beginning address of any 64K-byte memory segment. – offset address - any location within the 64K byte memory segment – E.g.: Beginning of memory segment? End location of memory segment? Location pointed by displacement/offset address? Logical address: Segment address (seg_add) and offset address (off_add) can be written as seg_add:off_add. – 1000:F000 - segment address of 1000H; an offset of F000H  Control Bus Control and timing information – Memory read/write signal – Interrupt request – Clock signals  Single Bus Problems Lots of devices on one bus leads to: – Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems Bus characteristics  Bus Types Dedicated – Separate data & address lines – functionally Dedication or Physical Dedication Multiplexed – Shared lines – Address valid or data valid control line – Advantage - fewer lines – Disadvantages More complex control Ultimate performance  Bus Arbitration Arbitration may be centralised or distributed Centralised Arbitration : – Single hardware device controlling bus access (Bus Controller or Arbiter). – May be part of CPU or separate. Distributed Arbitration : – Each module may claim the bus. – Control logic on all modules.  Timing Co-ordination of events on bus Synchronous – Events determined by clock signals – Control Bus includes clock line – A single 1-0 is a bus cycle – All devices can read clock line – Usually sync on leading edge – Usually a single cycle for an event Asynchronous – Event on a bus follows and depends on the occurrence of a previous event – mixture of slow and fast devices Data Transfer Type End of Lecture