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The ARM (Advanced RISC machine) Architecture T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R TM...

The ARM (Advanced RISC machine) Architecture T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R TM 1L D  ARM Ltd ◼ Founded in November 1990 ◼ Spun out of Acorn Computers ◼ Designs the ARM range of RISC processor cores ◼ Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. ◼ ARM does not fabricate silicon itself ◼ Also develop technologies to assist with the design-in of the ARM architecture ◼ Software tools, boards, debug hardware, application software, bus architectures, peripherals etc 39v10 The ARM Architecture TM 2 2  ARM Partnership Model 39v10 The ARM Architecture TM 3 3  ARM Powered Products 39v10 The ARM Architecture TM 4 4  Intellectual Property ◼ ARM provides hard and soft views to licencees ◼ RTL and synthesis flows ◼ GDSII layout ◼ Licencees have the right to use hard or soft views of the IP ◼ soft views include gate level netlists ◼ hard views are DSMs ◼ OEMs must use hard views ◼ to protect ARM IP 39v10 The ARM Architecture TM 5 5  Data Sizes and Instruction Sets ◼ The ARM is a 32-bit architecture. ◼ When used in relation to the ARM: ◼ Byte means 8 bits ◼ Halfword means 16 bits (two bytes) ◼ Word means 32 bits (four bytes) ◼ Most ARM’s implement two instruction sets ◼ 32-bit ARM Instruction Set ◼ 16-bit Thumb Instruction Set ◼ Jazelle cores can also execute Java bytecode 39v10 The ARM Architecture TM 6 6  Processor Modes ◼ The ARM has seven basic operating modes: ◼ User : unprivileged mode under which most tasks run ◼ FIQ : entered when a high priority (fast) interrupt is raised ◼ IRQ : entered when a low priority (normal) interrupt is raised ◼ Supervisor : entered on reset and when a Software Interrupt instruction is executed ◼ Abort : used to handle memory access violations ◼ Undef : used to handle undefined instructions ◼ System : privileged mode using the same registers as user mode 39v10 The ARM Architecture TM 7 7  ARM 7 ARCHITECTURE Features 32-bit RISC-processor core (32-bit instructions) 37 pieces of 32-bit integer registers (16 available) Thumb instruction set Pipelined (ARM7: 3 stages) Cached (depending on the implementation) Von Neuman-type bus structure (ARM7), Harvard (ARM9) Debug Interface Embedded ICE macrocell Jazelle DBX(Direct Bytecode eXecution) 8 / 16 / 32 -bit data types 7 modes of operation (usr, fiq, irq, svc, abt, sys, und) 39v10 The ARM Architecture TM 8 8  Pipelining 39v10 The ARM Architecture TM 10 10  Harvard architecture vs Von-Neumann architecture ◼ In Harvard architecture, the CPU is connected with both the data memory (RAM) and program memory (ROM), separately. ◼ In Von-Neumann architecture, there is no separate data and program memory. Instead, a single memory connection is given to the CPU. 39v10 The ARM Architecture TM 11 11  The Registers ◼ ARM has 37 registers all of which are 32-bits long. ◼ 1 dedicated program counter ◼ 1 dedicated current program status register ◼ 5 dedicated saved program status registers ◼ 30 general purpose registers ◼ The current processor mode governs which of several banks is accessible. Each mode can access ◼ a particular set of r0-r12 registers ◼ a particular r13 (the stack pointer, sp) and r14 (the link register, lr) ◼ the program counter, r15 (pc) ◼ the current program status register, cpsr Privileged modes (except System) can also access ◼ a particular spsr (saved program status register) 39v10 The ARM Architecture TM 12 12  Program Counter (r15) ◼ When the processor is executing in ARM state: ◼ All instructions are 32 bits wide ◼ All instructions must be word aligned ◼ Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned). ◼ When the processor is executing in Thumb state: ◼ All instructions are 16 bits wide ◼ All instructions must be halfword aligned ◼ Therefore the pc value is stored in bits [31:1] with bit undefined (as instruction cannot be byte aligned). ◼ When the processor is executing in Jazelle state: ◼ All instructions are 8 bits wide ◼ Processor performs a word access to read 4 instructions at once 39v10 The ARM Architecture TM 13 13  Development of the ARM Architecture 39v10 The ARM Architecture TM 14 14  Example ARM-based embedded System 39v10 The ARM Architecture TM 15 15