arm_inst.pdf

ARM Instruction Set Computer p Organization g z and Assemblyy Languages g g Yung-Yu Chuang with slides by Peng-Sheng Chen Introduction The ARM processor is easy to program at the assembly level level. (It is a RISC)...

ARM Instruction Set Computer p Organization g z and Assemblyy Languages g g Yung-Yu Chuang with slides by Peng-Sheng Chen Introduction The ARM processor is easy to program at the assembly level level. (It is a RISC) We will learn ARM assembly programming at the user level l l and d run it on a GBA emulator. l t ARM programmer model The state of an ARM system is determined by the content of visible registers and memory. memory A user-mode program can see 15 32-bit general- purpose registers i t (R0 (R0-R14), R14) program counter t (PC) and CPSR. Instruction set defines the operations that can change the state. Memory system Memory is a linear array of 0x00000000 00 bytes addressed from 0 to 0x00000001 10 232-1 20 0x00000002 Word, W d h half-word, lf d bbyte t 0x00000003 30 Little-endian 0x00000004 FF FF 0x00000005 FF 0x00000006 00 0 FFFFFFFD 0xFFFFFFFD 00 0xFFFFFFFE 00 0xFFFFFFFF Byte ordering Big Endian – Least significant byte has 0x00000000 00 highest address 0x00000001 10 Word address 0x00000000 20 0 00000002 0x00000002 Value: 00102030 30 0x00000003 Little Endian FF – Least significant byte has 0x00000004 FF lowest address 0x00000005 Word address 0x00000000 FF 0x00000006 Value: 30201000 00 0xFFFFFFFD 00 0xFFFFFFFE 00 0xFFFFFFFF ARM programmer model 0x00000000 00 0x00000001 10 R0 R1 R2 R3 20 0x00000002 R4 R5 R6 R7 0x00000003 30 FF R8 R9 R10 R11 0 00000004 0x00000004 FF R12 R13 R14 PC 0x00000005 FF 0x00000006 00 0xFFFFFFFD 00 0xFFFFFFFE 0 00 0xFFFFFFFF Instruction set ARM instructions are all 32-bit 32 bit long (except for Thumb mode). mode) There are 232 possible machine instructions. Fortunately they Fortunately, are structured. Features of ARM instruction set Load-store architecture 3 dd 3-address iinstructions i Conditional execution of every instruction Possible to load/store multiple registers at once Possible to combine shift and ALU operations in a single instruction Instruction set Data processing Data D movement Flow control Data processing They are move, arithmetic, logical, comparison and multiply instructions. instructions Most data processing instructions can process one off th their i operands d using i th the b barrell shifter. hift General rules: – All operands are 32-bit, coming from registers or literals. – The result, if any, is 32-bit and placed in a register (with the exception ti for f llongg multiply lti l which produces a 64-bit result) – 3-address 3 address format Instruction set MOV Rd, MOVCS R0, R1 @ if carry is set @ then R0:=R1 MOVS R0, #0 @ R0:=0 @ Z=1, , N=0 @ C, V unaffected Conditional execution Almost all ARM instructions have a condition field which allows it to be executed conditionally. movcs R0, 0 R1 1 Register movement immediate,register,shift MOV R0, R2 @ R0 = R2 MVN R0, 0 R22 @ R0 0 = ~R22 move negated t d Addressing modes Register operands ADD R0 R0, R1 R1, R2 Immediate operands a literal; most can be represented by (0..255)x22n 02 @ R2 unchanged g Example: 1010 0…0 0011 0000 Before R2=0xA0000030 R2 0xA0000030 After R0=0xE800000C R2=0xA0000030 Rotate right register MOV R0, R2, ROR #2 @ R0:=R2 rotate @ R2 unchanged g Example: 0…0 0011 0001 Before R2=0x00000031 R2 0x00000031 After R0=0x4000000C R2=0x00000031 Rotate right extended C register C MOV R0, R2, RRX @ R0:=R2 rotate @ R2 unchanged g Example: 0…0 0011 0001 Before R2=0x00000031, R2 0x00000031, C=1 C 1 After R0=0x80000018, C=1 R2=0x00000031 Shifted register operands Shifted register operands Shifted register operands It is possible to use a register to specify the number of bits to be shifted; only the bottom 8 bits of the register are significant. @ array i index d calculation l l ti ADD R0, R1, R2, LSL R3 @ R0:=R1+R2*2R3 @ fast multiply R2=35xR0 ADD R0, R0, R0, LSL #2 @ R0’=5xR0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0’ Multiplication MOV R1, #35 MUL R2 R2, R0 R0, R1 or ADD R0, 0 R0, 0 R0, 0 LSL #2 @ R0’=5xR0 0’ 5 0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0’ Shifted register operands Encoding data processing instructions 31 28 27 26 25 24 21 20 19 16 15 12 11 0 cond 00 # opcode S Rn Rd operand 2 destination register first operand register set condition codes arithmetic/logic function 25 11 8 7 0 1 # t #rot 8 bit iimmediate 8-bit di t immediate alignment 11 7 6 5 4 3 0 #shift Sh 0 Rm 25 immediate shift length 0 shift f type second operand register 11 8 7 6 5 4 3 0 Rs 0 Sh 1 Rm register shift length Arithmetic Add and subtraction Arithmetic ADD R0, R1, R2 @ R0 = R1+R2 ADC R0 R0, R1 R1, R2 @ R0 = R1+R2+C R1 R2 C SUB R0, R1, R2 @ R0 = R1-R2 SBC R0, R1, R2 @ R0 = R1-R2-!C RSB R0, R1, R2 @ R0 = R2-R1 R2 R1 RSC R0, R1, R2 @ R0 = R2-R1-!C -11 -128 128 127 0 -5 3 255 128 127 0 3-5=3+(-5) → sum 255 → C=1 → no borrow Arithmetic Arithmetic Setting the condition codes Any data processing instruction can set the condition codes if the programmers wish it to 64-bit addition R1 R0 ADDS R2, R2, R0 + R3 R2 ADC R3 R3, R3 R3, R1 R3 R2 Logical Logical AND R0, R1, R2 @ R0 = R1 and R2 ORR R0 R0, R1 R1, R2 @ R0 = R1 or R2 EOR R0, R1, R2 @ R0 = R1 xor R2 BIC R0, R1, R2 @ R0 = R1 and (~R2) bit clear: R2 is a mask identifying which bits of R1 will be cleared to zero R1=0x11111111 R2=0x01100101 BIC R0, R1, R2 R0=0x10011010 Logical Comparison These instructions do not generate a result, but set condition code bits (N (N, Z Z, C C, V) in CPSR CPSR. Often, a branch operation follows to change the program flow. flow Comparison compare CMP R1 R1, R2 @ set cc on R1-R2 compare negated CMN R1 R1, R2 @ set cc on R1+R2 bit test TST R1 R1, R2 @ set cc on R1 and R2 test equal TEQ R1 R1, R2 @ set t cc on R1 xor R2 Comparison Multiplication Multiplication MUL R0, R1, R2 @ R0 = (R1xR2)[31:0] Features: – Second S d operand d can’t ’t bbe iimmediate di t – The result register must be different from the first operand y – Cycles depends p on core type yp – If S bit is set, C flag is meaningless See the reference manual (4.1.33) (4 1 33) Multiplication Multiply-accumulate (2D array indexing) MLA R4 R4, R3 R3, R2 R2, R1 @ R4 = R3xR2+R1 M Multiply lti l with ith a constant t t can often ft b be more efficiently implemented using shifted register operand MOV R1, #35 MUL R2 R2, R0 R0, R1 or ADD R0, R0, R0, LSL #2 @ R0’=5xR0 RSB R2, R0, R0, LSL #3 @ R2 =7xR0’ Multiplication Multiplication Flow control instructions Determine the instruction to be executed next pc-relative offset within 32MB Flow control instructions Branch instruction B l b l label … label: … Conditional branches MOV R0, #0 loop: … ADD R0 R0, R0 R0, #1 CMP R0, #10 BNE loop Branch conditions Branches Branch and link BL instruction save the return address to R14 (lr) BL sub @ call sub CMP R1, #5 @ return to here MOVEQ R1, #0 … sub: … @ sub entry point … MOV PC, LR @ return Branch and link BL sub1 @ call sub1 … use stack to save/restore the return address and registers sub1: STMFD R13!, {R0-R2,R14} BL sub2 … LDMFD R13!, , { {R0-R2,PC} , } sub2: … … MOV PC PC, LR  Conditional execution CMP R0, #5 BEQ b bypass pass @ if (R0! (R0!=5) 5) { ADD R1, R1, R0 @ R1=R1+R0-R2 SUB R1, R1, R2 @ } bypass: … CMP R0,, #5 smaller and faster ADDNE R1, R1, R0 SUBNE R1 R1, R1 R1, R2 Rule of thumb: if the conditional sequence q is three instructions or less, it is better to use conditional execution than a branch. Conditional execution if ((R0==R1) && (R2==R3)) R4++ CMP R0, R1 BNE skip CMP R2, R3 BNE skip ADD R4, R4, #1 skip: … CMP R0 R0, R1 CMPEQ R2, R3 ADDEQ R4 R4, R4 R4, #1 Data transfer instructions Move data between registers and memory Three Th basic b i forms f – Single register load/store – Multiple register load/store – Single register swap: SWP(B), atomic instruction for semaphore Single register load/store Single register load/store No STRSB/STRSH since STRB/STRH stores both signed/unsigned i d/ i d ones Single register load/store The data items can be a 8-bit byte, 16-bit half- word or 32-bit 32 bit word. word Addresses must be boundary aligned. (e.g. 4’s multiple for LDR/STR) LDR R0, [R1] @ R0 := mem32[R1] STR R0, [R1] @ mem32[R1] := R0 LDR, , LDRB for 32,, 16,, 8 bits , LDRH, STR, STRH, STRB for 32, 16, 8 bits Addressing modes Memory is addressed by a register and an offset. LDR R0 R0, [R1] @ mem[R1] [R1] Three ways to specify offsets: – Immediate LDR R0, [R1, #4] @ mem[R1+4] – Register R i LDR R0, [R1, R2] @ mem[R1+R2] – Scaled register @ mem[R1+4*R2] [R1+4*R2] LDR R0, [R1, R2, LSL #2] Addressing modes Pre-index addressing (LDR R0, [R1, #4]) without ih a writeback i b k Auto-indexing addressing (LDR R0, [R1, #4]!) Pre-index with writeback calculation before accessing with a writeback Post-index addressing (LDR R0, [R1], #4) calculation l l ti after ft accessing i with ith a writeback it b k Pre-index addressing LDR R0, [R1, #4] @ R0=mem[R1+4] @ R1 unchanged nchanged LDR R0, [R1, ] R1 + R0 Auto-indexing addressing LDR R0, [R1, #4]! @ R0=mem[R1+4] @ R1 R1=R1+4 R1+4 No extra time;; Fast;; LDR R0, [R1, ]! R1 + R0 Post-index addressing LDR R0, R1, #4 @ R0=mem[R1] @ R1 R1=R1+4 R1+4 LDR R0,[R1], R1 R0 + Comparisons Pre-indexed addressing LDR R0 R0, [R1, [R1 R2] @ R0=mem[R1+R2] @ R1 unchanged Auto-indexing Auto indexing addressing LDR R0, [R1, R2]! @ R0=mem[R1+R2] @ R1 R1=R1+R2 R1+R2 Post-indexed addressing LDR R0, [R1], R2 @ R0=mem[R1] @ R1=R1+R2 Example Example Example Summary of addressing modes Summary of addressing modes Summary of addressing modes Summary of addressing modes Load an address into a register Note that all addressing modes are register- offseted Can we issue LDR R0 offseted. R0, Table? The pseudo instruction ADR loads a register with an address table:.word 10 … ADR R0, table Assembler transfer p pseudo instruction into a sequence of appropriate instructions sub r0 pc r0, pc, #12 Application ADR R1, table table loop loop: LDR R0 R0, [R1] R1 ADD R1, R1, #4 @ operations on R0 … ADR R1, , table loop: LDR R0, [R1], #4 @ operations on R0 … Multiple register load/store Transfer a block of data more efficiently. Used U d for f procedure d entry and d exit i ffor saving i and restoring workspace registers and the return t address dd For ARM7, 2+Nt cycles (N:#words, t:time for a word for sequential access). Increase interrupt latency since it can’t be interrupted. registers are arranged an in increasing order; see manual LDMIA R1, {R0, R2, R5} @ R0 = mem[R1] @ R2 = mem[r1+4] @ R5 = mem[r1+8] Multiple load/store register LDM load multiple registers STM store m multiple ltiple registers suffix meaning IA increase after IB increase before DA decrease after DB decrease before Addressing modes Multiple load/store register LDM Rn, {} IA: addr:=Rn IB: addr:=Rn+4 DA: addr:=Rn-#*4+4 DB: addr:=Rn-#*4 # For each Ri in IB: addr:=addr+4 DB: addr:=addr-4 Ri:=M[addr] IA: addr:=addr+4 Rn DA: addr:=addr-4 R1 : ! Rn:=addr R2 R3 Multiple load/store register LDM Rn, {} IA: addr:=Rn IB: addr:=Rn+4 DA: addr:=Rn-#*4+4 DB: addr:=Rn-#*4 # For each Ri in IB: addr:=addr+4 DB: addr:=addr-4 Ri:=M[addr] IA: addr:=addr+4 Rn DA: addr:=addr-4 : ! Rn:=addr R1 R2 R3 Multiple load/store register LDM Rn, {} IA: addr:=Rn IB: addr:=Rn+4 DA: addr:=Rn-#*4+4 DB: addr:=Rn-#*4 # For each Ri in IB: addr:=addr+4 R1 DB: addr:=addr-4 R2 Ri:=M[addr] R3 IA: addr:=addr+4 Rn DA: addr:=addr-4 : ! Rn:=addr Multiple load/store register LDM Rn, {} IA: addr:=Rn IB: addr:=Rn+4 DA: addr:=Rn-#*4+4 DB: addr:=Rn-#*4 # For each Ri in R1 IB: addr:=addr+4 R2 DB: addr:=addr-4 R3 Ri:=M[addr] IA: addr:=addr+4 Rn DA: addr:=addr-4 : ! Rn:=addr Multiple load/store register LDMIA R0, {R1,R2,R3} or LDMIA R0, {R1-R3} addr data 0x010 10 R0 R1: 10 0x014 20 R2: 20 0x018 30 R3: 30 0x01C 40 R0: 0x10 0x020 50 0x024 60 Multiple load/store register LDMIA R0!, {R1,R2,R3} addr data 0x010 10 R0 R1: 10 0x014 20 R2: 20 0x018 30 R3: 30 0x01C 40 R0: 0x01C 0x020 50 0x024 60 Multiple load/store register LDMIB R0!, {R1,R2,R3} addr data 0x010 10 R0 R1: 20 0x014 20 R2: 30 0x018 30 R3: 40 0x01C 40 R0: 0x01C 0x020 50 0x024 60 Multiple load/store register LDMDA R0!, {R1,R2,R3} addr data 0x010 10 R1: 40 0x014 20 R2: 50 0x018 30 R3: 60 0x01C 40 R0: 0x018 0x020 50 R0 0x024 60 Multiple load/store register LDMDB R0!, {R1,R2,R3} addr data 0x010 10 R1: 30 0x014 20 R2: 40 0x018 30 R3: 50 0x01C 40 R0: 0x018 0x020 50 R0 0x024 60 Example Example LDMIA r0!, {r1-r3} Example LDMIB r0!, {r1-r3} Application Copy a block of memory – R9 R9: address dd off th the source – R10: address of the destination – R11: R11 endd address dd off th the source loop: LDMIA R9!, {R0-R7} STMIA R10!, {R0-R7} CMP R9, R11 BNE loop Application Stack (full: pointing to the last used; ascending: grow towards increasing memory addresses) mode POP =LDM PUSH =STM Full ascending (FA) LDMFA LDMDA STMFA STMIB Full descending (FD) LDMFD LDMIA STMFD STMDB Empty ascending (EA) LDMEA LDMDB STMEA STMIA E t d Empty descending di ((ED)) LDMED LDMIB STMED STMDA LDMFD R13! R13!, {R2 {R2-R9} R9} @ used for ATPCS … @ modify R2-R9 STMFD R13!, {R2-R9} Example Swap instruction Swap between memory and register. Atomic operation preventing any other instruction from reading/writing to that location until it completes Example Application Process A OS Process B While (1) { While (1) { S=0/1 if (s==0) (s 0) { if (s==0) (s 0) { s=1; s=1; } } } } // use the // use the // resource // resource Software interrupt A software interrupt instruction causes a software interrupt exception exception, which provides a mechanism for applications to call OS routines. Example Load constants No ARM instruction loads a 32-bit constant into a register because ARM instructions are 32-bit 32 bit long. There is a pseudo code for this. Immediate numbers 31 28 27 26 25 24 21 20 19 16 15 12 11 0 cond 00 # opcode S Rn Rd operand 2 destination register first operand register v=n ror 2r set condition codes arithmetic/logic function 25 11 r 8 7 n 0 1 # t #rot 8 bit iimmediate 8-bit di t immediate alignment 11 7 6 5 4 3 0 #shift Sh 0 Rm 25 immediate shift length 0 shift f type encoding for second operand register 11 8 7 6 5 4 3 0 data processing Rs 0 Sh 1 Rm instructions register shift length Load constants Assemblers implement this usually with two options depending on the number you try to load. Load constants Assume that you want to load 511 into R0 – C Construct t t in i multiple lti l iinstructions t ti mov r0, #256 add dd r0,0 #255 – Load from memory; declare L511.word 511 ldr r0, L511 ldr r0, [pc, #0] # Guideline: if you can construct it in two instructions, do it; otherwise, load it. The assembler decides for you y ldr r0, =255 mov r0, 255 ldr r0, , =511 ldr r0, , [p [pc,, #4] ] PC-relative modes Impossible to use direct addressing encoding for data transfer instructions PC-relative addressing main: MOV R0, #0 ADR R1, a @ add r1, pc, #4 STR R0 R0, [R1] PC SWI #11 a:.word word 100.end fetch decode exec fetch decode exec fetch decode exec Instruction set