Kanaan Kano - Semiconductor Devices (1997, Prentice Hall) - libgen.li-174-199.pdf

chapter 6 FABRICATION TECHNOLOGY 6.0 INTRODUCTION The use of semiconductors has had a profo...

chapter 6 FABRICATION TECHNOLOGY 6.0 INTRODUCTION The use of semiconductors has had a profound impact on the electronics industry and t h e consequent introduction of integrated circuits has had a major impact on everyday life. The microminiaturization of electronics circuits and systems and their concomitant application to computers and communications represent major inno­ vations of the twentieth century. These have led to t h e introduction of new applica­ tions that were not possible with discrete devices. The simultaneous formation of m a n y integrated circuits on a single silicon wafer followed by t h e increase of t h e size of t h e wafer to a c c o m m o d a t e m a n y m o r e such circuits served to significantly reduce the costs while increasing the reliability of these circuits. W h e r e a s t h e electronics engineer was previously concerned with the design of circuits using discrete elements, the engineer is now involved with the ubiquitous interaction b e t w e e n t h e circuit and t h e fabrication process, which itself influences the circuit design, thus forming an integral design feedback loop. Design engineers are n o w r e q u i r e d to design the systems, the logic, the circuits, and t h e layout of the integrated circuits on a wafer. T h e ingenuity in the design of economically competi­ tive circuits that m e e t t h e r e q u i r e m e n t s of b o t h speed and power dissipation is partly a result of the engineer's expertise in the allocation of space on a silicon chip. R e a l estate on t h e wafer and on the chip has b e c o m e a p r i m e commodity. Before the student proceeds to the study of the operation and characteristics of o t h e r semiconductor devices, he or she should be aware of, first, the materials and t h e processes used in the fabrication of integrated circuits and devices, second, of the layout of t h e devices on a silicon chip, and, third, of the dimensions involved, in 156  Section 6.1 Why Silicon? 157 Figure 6.1 Illustration of wafer and chip. particular, in integrated circuits. T h e main reason for introducing the subject of fab­ rication early on is that while we use simple sketches to describe the o p e r a t i o n of the device in later chapters, the student will be cognizant of, and can visualize, the actual construction of the device so that she or he may better u n d e r s t a n d the p r o p ­ erties and t h e limitations of these devices. A p h o t o g r a p h of a wafer containing hun­ dreds of dice (chips) and a drawing of a chip are shown in Fig. 6.1. The identical 2 chips, each of which may vary in area from 10 to over 100 m m , may contain u p to several million devices. In this chapter, we will first describe the process by which boules or ingots of silicon are obtained. This process results in the formation of solid cylindrical-shaped ingots. It is from these that wafers are sawed off. Following this, we describe the various processes that are used in the fabrica­ tion of devices. Since we have already studied the P N junction diode in the previous chapter, we end this chapter by applying the processes to illustrate the fabrication of a diode, a capacitor, and a resistor for an integrated circuit. In C h a p t e r s 8 , 1 1 , and 12, wherein the other major devices are studied, we will apply these processes to the fabrication of a bipolar transistor, a metal-semiconduc­ tor field-effect transistor, and a metal-oxide-semiconductor field-effect transistor. 6.1 W H Y S I L I C O N ? Semiconductor devices are m a d e in one of two forms: either as single discrete units, such as a diode or a transistor, or in conjunction with other circuit elements making u p an integrated circuit. Integrated circuits may be monolithic, w h e r e b y transistors, diodes, resistors, and capacitors are fabricated and interconnected on the same sili­ con chip or they may b e hybrid. In hybrid circuits, some of the circuit elements are in discrete form and others are interconnected on a chip with the discrete elements connected externally to those formed on the chip. 158 Chapter 6 Fabrication Technology The fundamental processes in t h e fabrication of discrete devices and inte­ grated circuits are the same. In this chapter, we will explain and illustrate the various processes that are required to form the devices and the integrated circuits. The fabrication of semiconductor devices has b e e n based on t h e use of silicon as the p r e m i e r semiconductor. Two other semiconductors, germanium and gallium arsenide, present special p r o b l e m s while silicon has certain specific advantages not available with the others. A t 300K, silicon has a b a n d gap of 1.12eV, while germanium's b a n d gap is 0.66eV. Because of this small b a n d gap, t h e intrinsic carrier density of germanium at 13 3 Τ = 300K is about 2.5 X 10 cm. A t t e m p e r a t u r e s of about 400K, this density 15 3 b e c o m e s 1 0 c m ~ , which is c o m p a r a b l e to t h e lower range of doping densities used. This p r o p e r t y limits its use to low t e m p e r a t u r e applications at less than 350K. The o t h e r semiconductor of major interest is gallium arsenide. In spite of its attractive electrical properties, gallium arsenide crystals have a high density of crys­ tal defects, which limit t h e performance of devices m a d e from it. F u r t h e r m o r e , com­ p o u n d semiconductors, such as G a A s (in contrast to elemental semiconductors such as Si and G e ) are m u c h m o r e difficult to grow in single crystal form. B o t h silicon and g e r m a n i u m do not suffer, in t h e processing steps, from possible decomposition that may occur in c o m p o u n d semiconductors such as G a A s. O n the plus side, G a A s has a low-field electron velocity that is larger than sili­ con so that electron devices using G a A s are faster t h a n those using Si. Also, G a A s has a lower saturation electric field than Si so that G a A s devices have a smaller power-delay product. Devices m a d e from substrates of G a A s tend to have smaller parasitic capacitances, which contribute to their speed advantage over silicon devices. A n o t h e r advantage of G a A s results from its direct b a n d gap, which m a k e s it possible to provide certain functions not possible in Si, such as coherent and inco­ h e r e n t light emission. A major advantage of silicon, in addition to its a b u n d a n t availability in the form of sand, is that it is possible to form a superior stable oxide, S i 0 , which has 2 superb insulating properties and, as we shall see later, provides an essential and excellent ingredient in the fabrication and protection of devices. Lastly, at the present time, silicon remains the major semiconductor in the industry. 6.2 T H E P U R I T Y O F SILICON The starting form of silicon, which manufacturers of devices and integrated circuits use, is a circular slice k n o w n as a wafer. T h e wafers are cut from single cylindrical ingots of silicon, with wafer diameters, varying from 10 to 20cm and expected to reach 30cm in the not too distant future. The wafer thickness is of the order of sev­ eral h u n d r e d microns. L a r g e d i a m e t e r wafers are very cost-effective because of t h e larger n u m b e r of integrated circuits they accommodate. Silicon is found in a b u n d a n c e in n a t u r e as an oxide in sand and quartz. A num­ ber of processes are required to convert the sand into silicon wafers. To b e useful in  Section 6.2 The Purity of Silicon 159 fabrication, silicon must b e in crystalline form—very pure, free of defects, and uncontaminated. T h e r e is n o other industry that places d e m a n d s as severe as those required by the semiconductor industry on the purity of silicon. In the following discussion, we will d e t e r m i n e an estimate of t h e expected purity of silicon. We start with the expected results. Normally, and for the greatest n u m b e r of applications, the d o p a n t densities in 15 1 9 - 3 devices vary from 1 0 t o 1 0 c m. T o be effective, these densities must be very pre­ cisely controlled. Impurities that are inherently present in the silicon or that m a y b e accidentally introduced, w h e t h e r in the bulk (volume) form or o n the surface of the material, interfere to a serious extent with the operation of t h e fabricated devices. In o r d e r for the impurities to b e at a sufficiently low and acceptable level, their density 15 3 should b e n o greater than two or t h r e e orders of magnitude lower than 1 0 c m ~. A t 13 3 this level, t h e density of u n w a n t e d impurities should not exceed 1 0 c m ~. We deter­ 22 mined in C h a p t e r 1 that there are approximately 1 0 atoms per cubic centimeter in silicon. We are requiring, therefore, that there b e n o m o r e than one u n w a n t e d impu­ 9 rity in 1 0 silicon atoms. This is a purity of one in a billion. Silicon From S a n d Since we n e e d silicon in crystal form for integrated circuit fabrication, the question is: H o w d o we find it or obtain it? Silicon, as the element, is not found in nature. It is, however, found abundantly in n a t u r e in the form of silicon dioxide, which constitutes about 20 percent of t h e earth's crust. Silicon is commonly found as quartz or sand. Therefore, we have to first convert silicon dioxide into silicon. O n e might consider reducing S i O by the addition of hydrogen, but this is not z possible because S i O is a very stable c o m p o u n d. T h e r e are several m e t h o d s avail­ z able for obtaining silicon and t h e most c o m m o n is to first refine silicon dioxide chemically with carbon in an arc furnace at very high t e m p e r a t u r e s resulting in Si and C 0. The C O evaporates as a gas leaving impure silicon, which is 90-99 percent 2 z p u r e and is k n o w n as metallurgical grade silicon. The next step is to purify the sili­ con. To purify silicon, a c o m m o n m e t h o d is to first p r o d u c e silicon tetrachloride by burning the silicon: Si + 2 C € - » SiC( 2 4 Silicon tetrachloride is a liquid that can b e distilled and b e m a d e of very high purity. T h e SiC€ is subjected to hydrogen reduction to p r o d u c e silicon. M o r e com­ 4 monly, t h e metallurgical grade silicon is purified by combining it with hydrochloric acid to form trichlorosilane, S i H C €. The trichlorosilane is reduced by hydrogen to 3 form very p u r e silicon, k n o w n as semiconductor grade silicon, which is vapor deposited on high purity silicon rods. A t this stage, the solid is polycrystalline composed of m a n y small crystals (of submicron dimensions) having r a n d o m orientation and containing m a n y defects. 9 The silicon contains one u n w a n t e d impurity a t o m in about 10 atoms of silicon. The 160 Chapter 6 Fabrication Technology purity is excellent. For silicon to be used in the fabrication of devices, however, it must be nearly perfect and crystalline in nature. We, therefore, now n e e d to produce single crystals of silicon. This is d o n e by a m e t h o d k n o w n as crystal growth. Crystal growth consists of converting a r a n d o m oriented or polycrystalline material into one that is orderly and crystalline. T h e easiest a p p r o a c h is to melt silicon and let it freeze. O n e m e t h o d to carry this out is in a growth process k n o w n as the Czochralski process. In this process, crystalline silicon, to which a d o p a n t is added, is grown. 6.3 T H E C Z O C H R A L S K I G R O W I N G P R O C E S S The Melt and the Dopant The e q u i p m e n t setup for this process is shown in Fig. 6.2. To grow crystals, one starts with very p u r e semiconductor grade silicon, which is melted in a quartz-lined graphite crucible. The melt is held at a t e m p e r a t u r e of 1690K, which is slightly greater than the melting point (1685K) of silicon. The surrounding heaters and heat shield establish a carefully controlled t e m p e r a t u r e with the center of the melt being t h e coolest. Pull direction C__J5 Pull and rotate Seed holder Seed Solid-liquid interface Solid single crystal Ο ο ο ο ο ο ο ο ο α RF heating coil ο ο ο ο Rotate and lift Quartz crucible Figure 6.2 The Czochralski method for crystal growth and purification.  Section 6.3 The Czochralski Growing Process 161 A precisely controlled quantity of the dopant is added to the melt; added boron makes Ρ silicon; a d d e d p h o s p h o r o u s m a k e s Ν silicon. O n e assumes that t h e density of impurities to be added is determined accurately by the desired resulting conduc­ tivity. However, the p r o b l e m is not as simple as it m a y seem. W h e n a material freezes, the concentration of impurities incorporated in the solid is usually smaller than the concentration in the liquid. T h e ratio of the concentration of impurities in the solid, C , t o that in the liquid, C , is k n o w n as the equilibrium segregation coefficient k , 0 ( Q k = C /C ο ( T h e r e is also a limit t o the a m o u n t of impurity that can be added as the con­ centration in t h e melt must not exceed about 2 percent, otherwise single crystal growth is h a m p e r e d. This together with t h e segregation coefficient limit t h e a m o u n t of doping in the crystal. The following example illustrates the mass of a dopant required for a certain doping density. E X A M P L E 6.1 16 3 A silicon ingot that should contain 10 phosphorus atoms/cm is to be grown by the Czochralski method. a) Determine the concentration of phosphorus atoms in the melt to give the required con­ centration in the ingot. b) The crucible initially contains 50Kg of molten silicon. Determine how many grams of phosphorus should be added: 3 Given: for phosphorus k = 0.35, density of silicon = 2.53g/cm and atomic weight of Q 23 phosphorus = 30.975g/mole, Avogadro's number = 6.023 x 10 atoms/mole. Solution a) k = C /C C = 10 crrr , C = 2.85 Χ 10 atoms/cm Q Q p Q l6 3 ( )6 3 b) volume of silicon = 50 X 1072.53 = 1.976 X 1 0 W Number of phosphorus atoms = 2.85 Χ 10 X 1.976 X 10" = 5.63 Χ 10 16 20 s s > x 1 a l o m x Amount of phosphorus = ° " ' ; ^ W - * = 28.95mg. 6.023 χ 10 atoms/mole We observe that a very small amount of phosphorus, ~ 0.03g. is needed to dope 50Kg of silicon. It is important t o note that for a given impurity there is a m a x i m u m density of the impurity, at a given t e m p e r a t u r e , that is allowed in or can be absorbed by a crys­ tal. This m a x i m u m concentration is known as solid solubility. Because the solubility decreases with t e m p e r a t u r e , if an impurity is introduced at its m a x i m u m concentra­ tion and the t e m p e r a t u r e is reduced, t h e crystal precipitates the excess impurity to achieve equilibrium. S e e d Crystal After having set u p the melt, a seed crystal (a small highly perfect crystal), attached to a holder and possessing the desired crystal orientation, is dipped into t h e melt and a small portion is allowed to melt. Very slowly, t h e seed is rotated and pulled up 162 Chapter 6 Fabrication Technology while, at the same time, the crucible is r o t a t e d in the opposite direction. The molten semiconductor attaches itself to the seed and it b e c o m e s identical to the seed in structure and orientation. A s the seed is pulled up, the melted material that is attached to the seed solid­ ifies (freezes). Its crystal structure b e c o m e s the same as that of t h e seed and a larger crystal is formed. By this m e t h o d , cylindrical single crystal bars of silicon are p r o ­ duced. A s the molten silicon solidifies o n the seed, the purity of the silicon is improved as most of the impurities t e n d e d to remain in the liquid and melt as the melted silicon gradually solidifies. The desired silicon bar diameter is obtained by controlling b o t h the tempera­ ture and the pulling speed. In the final process, when the bulk of the melt has b e e n grown, the crystal diameter is decreased until t h e r e is a point contact with the melt. The resulting ingot is cooled and r e m o v e d to be m a d e into wafers. The ingots have diameters as large as 200mm, with latest ones approaching 300mm. The ingot length is of the o r d e r of 100cm. I n g o t Slicing a n d W a f e r Preparation The ingot surface is ground t h r o u g h o u t to an exact diameter and t h e t o p and bot­ t o m portions are cut off. Following this, circular wafers are sliced off t h e ingot with a high speed d i a m o n d saw. T h e wafer thicknesses vary from 0.4 to 1.0mm. Slicing t h e wafers to be used in the fabrication of integrated circuits is a proce­ d u r e that requires precision equipment. The object is to p r o d u c e slices that are per­ fectly flat and as s m o o t h as possible, with n o d a m a g e to the crystal structure. The wafers n e e d to b e subjected t o a n u m b e r of steps k n o w n as lapping, polishing, and chemical etching. T h e wafers are first lapped with a suitable abrasive, such as dia­ m o n d , to r e m o v e t h e irregularities introduced by the sawing. They are also chemi­ cally etched t o p r o d u c e flat and parallel surfaces and finally polished to a mirror-like finish. The wafers are cleaned, rinsed, and dried for use in t h e fabrication of discrete devices and integrated circuits. It is interesting t o n o t e that the final wafer thickness is about o n e third less t h a n that after the sawing. The growth of G a A s crystals is m u c h m o r e complex than that of silicon. The largest commercially available wafers are about 10cm in diameter. O n e reason for this is that the wafers are brittle and m a y crack. F u r t h e r m o r e , G a A s crystals contain a high concentration of crystal defects that can d e g r a d e the device yield signifi­ cantly. In the next several pages, we will explain and illustrate with sketches, w h e r e necessary and relevant, the major operations required for the fabrication of circuits and devices o n a wafer of silicon. Having d o n e that, we will apply t h e knowledge gained to t h e fabrication of a P N junction diode. A s we study the major devices in the chapters following, we will refer to the operations involved in their fabrication and illustrate the fabrication of a typical device.  Section 6.4 Fabrication Processes 163 6.4 FABRICATION P R O C E S S E S The category of processes that are used in the fabrication of devices and integrated circuits are t h e following: Oxidation Diffusion I o n Implantation Photolithography Epitaxy Metallizations and interconnections. We will now consider each process separately and apply some of these to t h e formation of a diode, in this chapter, and to the fabrication of transistors, in later chapters. T h e basic fabrication process is k n o w n as t h e planar process, in which the introduction of impurities and metallic interconnections is carried out from the t o p of t h e wafer. A major advantage of the planar process is that each fabrication step is applied to all identical circuits and devices on each of the m a n y wafers at t h e same time. It is i m p o r t a n t to initially emphasize that the fabrication requires an extremely clean environment in addition to the precise control of t e m p e r a t u r e and humidity. Thermal Oxidation The process of oxidation consists of growing a thin film of silicon dioxide on t h e sur­ face of t h e silicon wafer. In the planar process, all operations are carried out from the t o p surface. It b e c o m e s necessary to shield certain regions of the surface so that d o p a n t atoms, by diffusion or ion implantation, may be driven into o t h e r selected regions. T h e formation of a silicon dioxide layer is shown in Fig. 6.3 and its shielding effect is illustrated in Fig. 6.6. Silicon dioxide, as we shall see later, plays an impor­ tant role in making this possible. F u r t h e r m o r e , an S i O layer serves as a passivating z or protective layer o n the silicon surface to protect the devices during subsequent processing. The commonly used silicon dopants, such as boron, phosphorous, arsenic, and antimony, have very low diffusion coefficients (diffuse with great difficulty) in S i 0. 2 Because of this, S i O is used as a shield against infiltration of these dopants. O n the z other hand, these dopants diffuse very easily if the surface is silicon. Oxidation is accomplished by placing t h e silicon wafers vertically into a quartz b o a t in a quartz tube, which is slowly passed through a resistance-heated furnace, in t h e presence of oxygen, operating at a t e m p e r a t u r e of about 1000°C. The oxidizing agent m a y b e dry using dry oxygen or wet using a mixture of water vapor and oxy­ gen. The oxide growth rate in the dry process is m u c h slower but it produces an oxi­ dized layer that has excellent electrical properties. T h e whole operation is 164 Chapter 6 Fabrication Technology (b) Figure 6.3 (a) Thermal oxidation system and (b) growth of Si0.2 controlled by microprocessors, which m o n i t o r b o t h the gas flow sequence and the furnace t e m p e r a t u r e. A t h e r m a l oxidation system, together with an example of S i 0 2 growth, are shown in Fig. 6.3. A silicon surface oxidizes very rapidly so that even at r o o m t e m p e r a t u r e a layer of silicon dioxide about 2nm thick is p r o d u c e d on the wafer. In the thermal oxidation process, the thickness of the oxide varies from 0.1 for VLSI gate oxide to one micron. F r o m a consideration of densities and relative molecular weights of Si and S i 0 , an oxide film of thickness x consumes 0.44JC of the silicon. This relation­ 2 Q 0 ship is d e t e r m i n e d in the example that follows. E X A M P L E 6.2 Determine the thickness of silicon that is consumed when a silicon dioxide layer of thickness x 0 is grown on the surface by thermal oxidation. Solution The volume of one mole of Si or S i 0 is the ratio of its molecular weight to its density, 2 determined as, 60.08g/mole „„„„ , 3 the volume of 1 mole of SiO, = 2 ,, ° , , = 27.23 cm 3 2.21g/cm the volume of 1 mole of Si = , — » - = 12.055 cm 2.33g/cm Since 1 mole of SiO uses up 1 mole of silicon over the same area, we have z  Section 6.4 Fabrication Processes 165 volume of 1 mole of silicon thickness of Si X area volume of 1 mole of S i 0 2 thickness of S i 0 X area 2 thickness of Si 12.055 = 0.44 "27.23 ο Thus, to grow 200 Angstroms of S i 0 , a layer of 88 Angstroms of silicon is used up. 2 O n c e the layer of S i O has b e e n formed on the surface of t h e wafer, it is selec­ z tively r e m o v e d (etched) from those surfaces where impurities are to b e introduced and k e p t as a shield, for the underlying silicon surface, where n o dopants are to b e allowed. Oxide layers are relatively free from defects and provide stable and reliable electrical properties. Etching Techniques Etching is the process of selective removal of regions of a semiconductor, metal, or silicon dioxide. T h e r e are two types of etchings: wet and dry. In wet etching, the wafers are immersed in a chemical solution at a p r e d e t e r m i n e d t e m p e r a t u r e. In this process, the material to be etched is r e m o v e d equally in all directions so that some material is etched from regions where it is to be left. This becomes a serious p r o b l e m when dealing with small dimensions. In dry (or plasma) etching, the wafers are immersed in a gaseous plasma cre­ ated by a radio-frequency electric field applied to a gas such as argon. T h e gas breaks d o w n and becomes ionized. Electrons are initially released by field emission from an electrode. These electrodes gain kinetic energy from the field, collide with, and transfer energy to the gas molecules, which results in generating ions and elec­ trons. The newly g e n e r a t e d electrons collide with other gas molecules and the avalanche process continues t h r o u g h o u t the gas, forming a plasma. The wafer to be etched is placed on an electrode and is subjected to the b o m b a r d m e n t of its surface by gas ions. A s a result, atoms at or near the surface to be etched are r e m o v e d by the transfer of m o m e n t u m from the ions to the atoms. Diffusion This process consists of t h e introduction of a few tenths to several micrometers of impurities by the solid-state diffusion of dopants into selected regions of a wafer to form junctions. Most of these diffusion processes occur in two steps: t h e predeposi­ tion and the drive-in diffusion. In the predeposition step, a high concentration of d o p a n t atoms are introduced at the silicon surface by a vapor that contains the d o p a n t at a t e m p e r a t u r e of about 1000°C. M o r e recently, a m o r e accurate m e t h o d of predeposition, to b e explained later, and k n o w n as ion implantation, is used. A t t h e t e m p e r a t u r e of 1000°C, silicon atoms move out of their lattice sites cre­ ating a high density of vacancies and breaking the b o n d with the neighboring atoms. The impurity atoms, which are incident on the surface, move into the silicon because 166 Chapter 6 Fabrication Technology Ρ substrate depth into Ρ substrate Figure 6.4 N-Impurity distributions into P-substrate, for predeposition and drive- in diffusion. of their concentration gradient and into the locations that the silicon atoms vacated. Predeposition tends to produce, near the silicon surface, a shallow but heavily d o p e d layer. The second step of diffusion, drive-in, is used to drive t h e impurity atoms d e e p e r into the surface, without adding any m o r e impurities, thus reducing the surface concentration of the dopant. A sketch of the resulting impurity distribu­ tions is shown in Fig. 6.4. C o m m o n dopants are boron for P-type layers and phosphorus, antimony, and arsenic for N-type layers. Diffusion, however, is rarely performed using the p u r e ele­ m e n t s themselves. R a t h e r , c o m p o u n d s of the elements are used and impurities may be introduced from either solid, liquid, or gaseous sources. B o r o n and p h o s p h o r u s have two desirable properties: (1) they have a high dif­ fusion rate (diffuse easily and quickly) into silicon and low diffusion rate in S i 0 2 and (2) they are b o t h highly soluble in silicon. We refer to S i O since, prior to carry­ z ing out the process of diffusion, windows are o p e n e d , in a previously deposited layer of S i 0 , for the impurities to diffuse in. The o p e n windows are in silicon but the 2 adjacent regions are shielded with silicon dioxide. The process of window opening is covered later. A typical a r r a n g e m e n t of t h e process of diffusion is shown in Fig. 6.5. The wafers are placed in a quartz furnace t u b e that is heated by resistance heaters sur­ rounding it. So that t h e wafers may b e inserted a n d r e m o v e d easily from t h e fur­ nace, they are placed in a slotted quartz carrier k n o w n as a boat. The wafers are m o u n t e d on their side, as illustrated in t h e figure. To introduce a p h o s p h o r u s dopant, as an example, p h o s p h o r u s oxychloride ( P O C l ) is placed in a container either inside the quartz tube, in a region of rela­ 3 tively low t e m p e r a t u r e , or in a container outside the furnace at a t e m p e r a t u r e that helps maintain its liquid form. For a Ρ dopant, b o r o n is used. The p r o p e r vapor pres­ sure is maintained by a control of t h e t e m p e r a t u r e.  Section 6.4 Fabrication Processes 167 resistance heaters quartz furnace tube quartz tube Vent end caps Liquid impurity source silicon wafers Figure 6.5 Physical layout of equipment used in diffusion. Nitrogen and oxygen gas are m a d e to pass over the container. These gases carry the d o p a n t vapor into the furnace, where t h e gases are deposited o n t h e sur­ face of t h e wafers. These gases react with the silicon, forming a layer on the surface of t h e wafer that contains silicon, oxygen, and phosphorus. A t the high t e m p e r a t u r e of the furnace, p h o s p h o r u s diffuses easily into t h e silicon. So that the d o p a n t may b e diffused d e e p e r into t h e silicon, the drive-in step follows. This is d o n e at a higher t e m p e r a t u r e of about 1100°C inside a furnace, simi­ lar to that used for predeposition, except that n o d o p a n t is introduced into the fur­ nace. T h e higher t e m p e r a t u r e causes t h e d o p a n t atoms to m o v e into t h e silicon m o r e quickly. Diffusion d e p t h is controlled by t h e time and t e m p e r a t u r e of the drive-in process. By precise control of the time and t e m p e r a t u r e (to within 0.25°C), accurate junction depths of fraction of a micron can b e obtained. Diffusion of d o p a n t into silicon is illustrated in Fig. 6.6. phosphorus dopant atoms deposited silicon dioxide Ρ semiconductor silicon SiO, dopant atoms diffuse in silicon but not in S i 0 2 Figure 6.6 Diffusion of dopant atoms in silicon. 168 Chapter 6 Fabrication Technology Expressions f o r t h e Diffusion of D o p a n t Concentration The process of diffusion of dopants is similar to that of the diffusion of holes and electrons that was discussed in C h a p t e r 4. We will relate expressions for the rate of d o p a n t diffusions. First, we define relevant terms: C = d o p a n t concentration in c m " at surface (x = 0). 3 χ = diffusion depth into t h e substrate (cm). t = duration of diffusion (s). 2 klT D = diffusion coefficient ( c m / s ) α exp~ , k is a constant. L = diffusion length = Vz)i. C(x,t) = d o p a n t concentration at depth χ and time t. Assuming that the diffusion coefficient is i n d e p e n d e n t of doping concentra­ tion, the diffusion equation is given by dC/dt = £>0 (6.1) By using the appropriate b o u n d a r y conditions, it can b e shown that the doping concentration C after the predeposition v step at a d e p t h χ and after time t is given v by QOcii) = C, erfc (x/V4D t )i l (6.2) w h e r e the error function a n d the error function c o m p l e m e n t are defined as erf(x) = 2/VTT f e^dy (6.3) Jo and erfc(x) = 1 - e r f ( χ ) (6.4) These functions are tabulated in mathematical handbooks. We list below a few of their properties: erf(0) = 0 erf(OO) = 0 dx j eric(x)dx = 1/VTT Jo The expression for C after the drive-in diffusion becomes 1 C (x,t ) 2 2 = C (2/JT s \fDytjD t ) 2 2 e-* '™^ (6.5) Sample calculations and plots are shown in Fig. 6.7 for p h o s p h o r u s predeposition at 1000°C for 8 minutes followed by a drive-in diffusion at 1250°C for 32 minutes. T h e  Section 6.4 Fabrication Processes 169 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 depth χ in μηι Figure 6.7 Impurity profiles for predeposition and drive-in diffusion. 1 4 2 relevant diffusion coefficients at the given t e m p e r a t u r e s are Ό = 2.5 X 10 γ cm /s 12 2 21 3 and D = 2.5 X 1 0 ~ c m / s and the concentration at χ = 0 is C = 1 0 c m ~. n Ion Implantation This is a process of introducing d o p a n t s into selected areas of the surface of the wafer by b o m b a r d i n g the surface with high-energy ions of the particular dopant. To generate ions, such as those of phosphorus, an arc discharge is m a d e to occur in a gas, such as phosphine ( P H ) , that contains t h e dopant. T h e ions are then 3 accelerated in an electric field so that they acquire an energy of about 20keV and are passed through a strong magnetic field. Because during t h e arc discharge u n w a n t e d impurities may have b e e n generated, the magnetic field acts to separate these impurities from t h e d o p a n t ions based on the fact that the a m o u n t of deflec­ tion of a particle in a magnetic field d e p e n d s on its mass. Following the action of the magnetic field, the ions are further accelerated so that their energy reaches several h u n d r e d keV, w h e r e u p o n they are focused on and strike the surface of the silicon wafer. A t this time, t h e ion current is of the order of 1mA. A s is the case with diffusion, the ion b e a m is m a d e to p e n e t r a t e only into selected regions of the wafer by a process of masking, which will be discussed later. 170 Chapter 6 Fabrication Technology O n entering the wafer, the ions collide with electrons and with nuclei of silicon atoms, and lose their energy. The d e p t h of p e n e t r a t i o n is about 0.1 to 1 micron. The higher the energy of t h e ions and t h e smaller their mass, the greater is the depth of penetration. Ion implantation has t h e following advantages: D o p i n g levels can b e precisely controlled since the incident ion b e a m can b e accurately m e a s u r e d as an electric current. T h e d e p t h of the d o p a n t can b e easily regulated by control of t h e incident ion velocity. It is capable of very shallow penetrations. E x t r e m e purity of the d o p a n t is guaranteed. The doping uniformity across t h e surface can b e accurately controlled. Because t h e ions enter the solid as a directed b e a m , t h e r e is very little spread of the b e a m , thus t h e doping area can b e clearly defined. Since this is a low-temperature process, t h e m o v e m e n t of impurities is mini­ mized. This process has o n e major shortcoming in that it may create considerable crystal d a m a g e because of t h e collisions of the high energy ions with t h e silicon. T h e r e are two types of collisions: First, electronic collisions take place b e t w e e n the incident electrons and t h e target atoms; second, nuclear collisions occur involving the nuclei of t h e incident and target atoms. Such d a m a g e results in inferior perfor­ mance of devices m a d e by this process. The d a m a g e may b e so extensive that it transforms the silicon from a crystalline to an a m o r p h o u s structure (Sec. 1.1). If t h e d a m a g e is not extensive, the lattice structure is restored by the process of annealing. In one process, k n o w n as furnace annealing, the wafer is h e a t e d in an inert a t m o s p h e r e at a t e m p e r a t u r e of 600 to 1000°C for about 30 minutes. This restores t h e crystalline a r r a n g e m e n t of t h e silicon. In a n o t h e r process, k n o w n as rapid t h e r m a l annealing ( R T A ) , optical radiant energy is generated and delivered to t h e surface of the wafer. The energy is gener­ ated by a tungsten-halogen l a m p at a wavelength of 0.3 to 4 micrometers in a quartz enclosure. Because of the n a t u r e of the process, the quartz walls do not acquire the light energy that is directed at the wafer and thus t h e wafer is not in t h e r m a l equilib­ rium with the walls of the system. A s a result, this process serves to considerably reduce t h e annealing time c o m p a r e d to that required in the furnace. A n o t h e r shortcoming of ion implantation is t h e investment in t h e e q u i p m e n t mainly because of its complexity. Photomask Generation The whole process of integrated circuit fabrication consists of identifying selected regions of each circuit (or dies) of t h e wafer surface into which identical d o p a n t or metallic interconnections are m a d e , while protecting the other regions of the wafer surface. To carry out one of t h e m a n y processes of oxidation, diffusion, ion implanta­ tion, or epitaxy, a separate mask or mini mask is required for each operation whose  Section 6.4 Fabrication Processes 171 function is to expose t h e selected regions and protect t h e others. T h e r e m a y b e hun­ dreds of identical dice (or ICs) on a wafer with each circuit containing h u n d r e d s of thousands, or millions, of devices. Identical steps are carried out simultaneously for each process, such as t h e diffusion of the Ν regions of a diode on one or several cir­ cuits, to b e r e p e a t e d over the whole wafer. For each process, a separate mask is needed. T h e mask production starts with a drawing using a computer-assisted graphics system with all the information about t h e drawing stored in digital form. C o m m a n d s from t h e c o m p u t e r are p r e p a r e d that drive a p a t t e r n generator, which uses an elec­ tron b e a m to write (photoengrave) the particular pattern, for one or several dice, on a glass plate covered with a thin c h r o m i u m film. W h e n t h e glass plate is p r e p a r e d for one or several dice on the wafer, it is k n o w n as a reticle. A mask usually refers to a glass plate that contains a p a t t e r n for t h e whole wafer. The reticle p a t t e r n is p r o ­ jected o n t o the wafer and a wafer stepper is used that reduces the reticle circuit onto the photoresist-covered (see next section) wafer that steps across over t h e surface until the entire array of circuits is built up. The use of a single mask for all t h e circuits on a wafer is not feasible for print­ ing very small ( < 1 μ η ι ) features because of alignment p r o b l e m s resulting from t h e heat that t h e wafer is exposed to, which causes slight distortion of the surface. Such systems are still in use, however, for fabricating simple logic circuits and analog devices such as L E D s. Photolithography In this process, the image on the reticle is transferred to t h e surface of t h e wafer. This is d o n e to o p e n identical windows so that t h e diffusion process, for example, may t a k e place in all identical regions of t h e same I C and for all ICs o n the wafer. A s an illustration, we assume that t h e first reticle is used over an oxidized surface. To transfer t h e pattern, the wafer is coated with a light-sensitive p h o t o e m u l - 3 sion, k n o w n as photoresist. By applying about 1cm of the liquid to the wafer surface and spinning the wafer very rapidly, a uniform film, about 1 micrometer thick, of photoresist is formed over t h e oxidized surface of the wafer. After this, the following steps, also shown in Fig. 6.8, are t a k e n to o p e n a window on the wafer: 1. The wafer is b a k e d at 100°C to solidify the resist on the wafer. 2. The reticle is placed o n t h e wafer and aligned by c o m p u t e r control. 3. The reticle is exposed to ultraviolet light with t h e transparent parts of the reti­ cle passing the light onto the wafer. T h e photoresist u n d e r t h e o p a q u e regions of the reticle is unaffected. 4. The exposed photoresist is chemically r e m o v e d by dissolving it in an organic solvent and exposing the silicon dioxide u n d e r n e a t h. This is a process very simi­ lar to that used in developing photographic film. 5. The exposed silicon dioxide is t h e n etched away using hydrofluoric acid, which dissolves silicon dioxide and not silicon. T h e regions u n d e r t h e o p a q u e part of the reticle are still covered by the silicon dioxide and t h e photoresist. 172 Chapter 6 Fabrication Technology SiO, Ρ silicon substrate and oxide film substrate '/////////////////////. -* positive photoresist SiO, photoresist applied substrate 1 II II II II It 1 mask mask placed above photoresist and UV '////////////////////, light directed at it SiO, substrate V////////A photoresist etched SiO, away under transparent regions of mask substrate ////////// '////////// SiO etched z SiO, away substrate SiO, remaining photoresist etched substrate away Figure 6.8 Steps in oxidation and window opening. 6. The photoresist u n d e r the o p a q u e regions of the reticle is stripped using a p r o p e r solvent and the silicon dioxide is exposed. All surfaces are protected except those covered by silicon only in which diffu­ sion or ion implantation is to t a k e place. The surfaces covered by silicon dioxide do not permit any entry of dopants. T h e photoresist used in this discussion is labeled a positive resist, whereby windows are o p e n e d wherever the ultraviolet light passes through the transparent parts of t h e mask. Negative resist is also used and remains on t h e surface, which is exposed to U V light, and windows are o p e n e d u n d e r t h e o p a q u e parts of the mask. T h e r e is a practical limit, at linewidths of about 1-2 micrometers, to using ultraviolet light. The printing of smaller features can b e accomplished by using very short wavelength radiation such as electron-beam or x-ray lithography.  Section 6.4 Fabrication Processes 173 We indicated earlier that the reticle or mask is placed in direct contact with the wafer. It may b e possible that t h e wafer has few irregular particles at the surface of the crystal or it may have some dust particles. These particles stick to the mask and cause defects in the surface of each successive operation. This p r o b l e m is cured by a process k n o w n as proximity printing, wherein the mask is separated from the wafer by a distance of about 10-20 micrometers. Epitaxial G r o w t h Epitaxy is the process of the controlled growth of a crystalline d o p e d layer of silicon on a single crystal substrate. T h e processes of diffusion and ion implantation, which w e r e earlier described, p r o d u c e a layer at the surface that is of higher doping den­ sity t h a n that which existed before the d o p a n t was added. It is not possible by these m e t h o d s to produce, at the surface, a layer of lower concentration than exists there. This can, however, b e accomplished by the m e t h o d of epitaxy. In the processes of diffusion and ion implantation, a d o p a n t is driven into a substrate of d o p e d silicon. In epitaxy, a layer of d o p e d silicon is deposited on t o p of the surface of the sub­ strate. Normally, this single crystal layer has different type doping from that of the substrate. + Epitaxy is used to deposit Ν on N silicon, which is impossible to accomplish by diffusion. It is also used in isolation b e t w e e n bipolar transistors wherein N~ is deposited on P. It may also b e used to improve the surface quality of an Ν substrate by depositing Ν material over it. The system for growing an epitaxial layer is shown in Fig. 6.9. In this system, silicon wafers are placed in a long boat-shaped crucible m a d e of graphite. The b o a t is placed in a long cylindrical quartz tube, which has inlets and RF heating coil gas valve and flow gauge vent ™ so m cl ϋ χ χ ζ χ χ - temperature bath Χ £ SiCI Figure 6.9 System for growing an epitaxial layer. 174 Chapter 6 Fabrication Technology outlets for the gases. The t u b e is h e a t e d by induction using t h e heating coils w o u n d a r o u n d the tube. All the chemicals that are introduced and that take part in the reactions are in the form of gases, hence the process is k n o w n as Chemical Vapor Deposition ( C V D ). The epitaxial layer is grown from t h e vapor phase onto the silicon, which is in the solid state. T h e thickness of the layer varies from 3 to 30 microns and the thickness of t h e layer and its doping content are controlled to an accuracy of less than 2 percent. The reactions are carried out at a t e m p e r a t u r e of approximately 1200°C. T h e high t e m p e r a t u r e is necessary so that t h e d o p a n t atoms can acquire a sufficient a m o u n t of energy to allow t h e m to m o v e into the crystal to form covalent b o n d s and b e c o m e an extension of the single crystal lattice. Because the layer is grown o n the substrate, epitaxy is a growth technique w h e r e the crystal is formed without reaching t h e melting point of silicon. We list below, and with reference to Fig. 6.7, the sequence of operations involved in t h e process: 1. H e a t wafer to 1200°C. 2. Turn o n H to reduce t h e S i O on t h e wafer surface. 2 z 3. Turn on anhydrous H C € to vapor-etch t h e surface of t h e wafer. This removes a small a m o u n t of silicon and other contaminants. 4. Turn off H C C 5. D r o p t e m p e r a t u r e to 1100°C. 6. Turn on silicon tetrachloride (SiC€ ). 4 7. I n t r o d u c e dopant. A n u m b e r of different chemical reactions can b e used to deposit t h e epitaxial layer. Silane ( S i H ) or SiCt? can b e used with t h e following reactions: 4 4 S i H -> Si + 2 H 4 2 SiC€ + H -> Si + 4 H C € 4 2 A silicon layer can b e p r o d u c e d from silane by the addition of heat, while sili­ con tetrachloride requires a reduction by hydrogen. To grow a layer of N-type silicon, very small a m o u n t s of impurities, such as P H , A s H , or S b H , are introduced simultaneously with the gases. D i b o r a n e ( B H ) 3 3 3 2 g is used to form a P-layer of silicon. D u r i n g the epitaxial layer deposition, t h e d o p a n t atoms d e c o m p o s e and they b e c o m e part of the layer. Thus, epitaxy provides a m e a n s for accurately controlling t h e doping profile in o r d e r to optimize t h e performance of devices and circuits. It is extremely important to r e p e a t o n e major consideration in t h e p r e p a r a t i o n of processes and devices, namely that t h e wafers must b e very smooth and clean. Dirt particles and irregularities can have damaging effects on t h e properties of the devices. A s indicated earlier, and in all these operations, t h e wafers are thoroughly cleaned before they are placed in a boat. O n c e inside t h e quartz tube, the cleaning process is carried out by using nitrogen to flush the air out and hydrochloric acid is m a d e to pass over the wafers in o r d e r to etch away a very thin layer of the surface.  Section 6.4 Fabrication Processes 175 M e t a l l i z a t i o n a n d Interconnections After all semiconductor fabrication steps of a device or of an integrated circuit are completed, it b e c o m e s necessary to provide metallic interconnections for the inte­ grated circuit and for external connections to b o t h the device and to the IC. The r e q u i r e m e n t that must b e m e t by t h e interconnections is that they have low resis­ tance to minimize b o t h the voltage drops on t h e lines as well as the capacitances b e t w e e n t h e lines so as to reduce delay times. The connections must also m a k e ohmic contacts to semiconductors in t h e devices such as the Ρ and Ν regions of a P N junction diode. A n ohmic contact is one that exhibits a very low resistance, allowing currents to pass easily in b o t h directions through t h e contact. The high conductivity of aluminum m a k e s it t h e metal of obvious choice, par­ ticularly in silicon-based devices. It also has the following advantages: 1. easy to e v a p o r a t e 2. can be easily etched 3. not expensive 4. adheres well to silicon dioxide T h e r e are a variety of m e t h o d s for depositing aluminum on silicon substrates, and we shall briefly present t h r e e c o m m o n methods, which are: resistance heating, electron b e a m heating, and sputtering. In resistance heating, the source of the h e a t e d e l e m e n t and the silicon substrate are located in an evacuated chamber. The source is a small piece of aluminum attached to a coil of tungsten, which serves as the heater. The h e a t e d filament with a high melting point remains solid while the a l u m i n u m (with a small addition of silver or copper) is vaporized. The aluminum molecules travel to the substrate w h e r e they condense, depositing an aluminum layer o n the surface of the silicon. A photolithographic masking and etching m e t h o d , using a phosphoric acid ( H P 0 ) solution or a dry etching technique, is 3 4 used to r e m o v e the metal from regions w h e r e it is not wanted. A typical intercon­ nection b e t w e e n two diffused layers is shown in Fig. 6.10. A n o t h e r m e t h o d of generating vaporized aluminum is to place the aluminum in a crucible into a v a c u u m c h a m b e r together with t h e substrate. T h e aluminum is diffusions Figure 6.10 An aluminum interconnection between two diffused silicon regions. 176 Chapter 6 Fabrication Technology subjected to a high intensity electron b e a m formed by an electron gun, which vapor­ izes the a l u m i n u m that travels to t h e wafer. By t h e use of a mask and photolithogra­ phy, the a l u m i n u m is deposited on the identified regions on the wafer surface. In t h e sputtering process, t h e material to b e deposited is placed in a container maintained at low pressure in t h e vicinity of the substrate. T h e material to be deposited is labeled the cathode or target, while the a n o d e is the substrate. A D C or a radio-frequency high voltage is applied b e t w e e n a n o d e and cathode. This high voltage ionizes the inert gas in the chamber. The ions are accelerated to the cathode (in this o p e r a t i o n the a n o d e is usually g r o u n d e d ) where, by impact with the alu­ m i n u m target, atoms of aluminum are vaporized. A gas of aluminum atoms is gener­ ated and deposited on t h e surface of the wafer. Following the deposition of aluminum, the silicon wafers are placed in a fur­ nace to solidify the connections so that low resistance metallic contacts are made. The interconnections b e t w e e n elements of an integrated circuit are m a d e by aluminum lines having a thickness of about 0.5μπι. These are laid on t o p of the sili­ con dioxide layer, which covers the surface of the wafer. By using photolithography, openings are m a d e in the silicon dioxide so that the aluminum layer is connected to the silicon or to t h e ohmic contact on the silicon. In very complicated integrated cir­ cuits, it is necessary to have two or three vertically stacked layers of interconnec­ tions separated by silicon dioxide layers. The interconnecting lines terminate at aluminum pads from which connections to the outside are made. The connections from t h e chips to the outside world are p r o d u c e d by the met­ allization p a t t e r n a r o u n d t h e periphery of the chip. These are k n o w n as bonding pads and they are connected by wires to the package, as shown in Fig. 6.11. The bonding pads are about 100>m square and the bonding wires are m a d e of gold with a diameter of about 25μπι. Following these connections, the individual dice are encapsulated and hermetically sealed in a variety of packages. Figure 6.11 Typical die package. Source: leads J. Mayer and S. Lau, Electronic Materials Science: For Integrated Circuits in Si and GaAs, Macmillan (1990).  Section 6.5 Planar PN Junction Diode Fabrication 177 It is i m p o r t a n t to maintain t h e resistance of the interconnections to small val­ ues. A large value for this resistance combined with parasitic capacitances can result in a time constant R C , which may end up, in a superfast device, to b e the limiting factor in the overall speed of a circuit. O h m i c Contacts It cannot be assumed that depositing aluminum on a d o p e d semiconductor forms a very good ohmic contact. A n ideal ohmic contact exhibits a perfectly linear relation­ ship b e t w e e n current and voltage with t h e plotted current-voltage characteristic passing through the origin. In certain cases, and as we shall discuss in later chapters, a contact b e t w e e n aluminum and a semiconductor may result in a rectifying contact having I-V characteristics of a diode, whereby current conduction is only in one direction. 16 3 O n P-type silicon having a concentration of 1 0 c m , or m o r e , aluminum forms a good ohmic contact. However, aluminum on lightly d o p e d N-type silicon forms a rectifying contact. In o r d e r to prevent the formation of such a contact, an + N diffusion is placed over t h e N-type silicon. 6.5 P L A N A R P N J U N C T I O N D I O D E F A B R I C A T I O N To illustrate t h e various steps in the fabrication of a discrete P N junction diode, we show in Fig. 6.12 a series of drawings that include most of the processes discussed earlier. We list below t h e various steps in t h e fabrication of a P N junction diode. It is important to indicate here that in integrated circuits, where all interconnections and device terminals are made at the surface, a diode is formed from a bipolar transistor by placing a short-circuit between two of the three terminals of the transistor (collec­ tor to base). Figure Process Description + (a) A n N substrate grown by the Czochralski process is t h e starting metal ~ 150μπι thick. (b) A layer of N-type silicon (1-5 μηι) is grown on the substrate by epitaxy. (c) Silicon dioxide layer deposited by oxidation. (d) Surface is coated with photoresist (positive). (e) Mask is placed on surface of silicon, aligned, and exposed to U V light. (f) Mask is removed, resist is removed, and S i O u n d e r the exposed resist is z etched. (g) B o r o n is diffused to form Ρ region. B o r o n diffuses easily in silicon but not in S i 0. 2 (h) Thin aluminum film is deposited over surface. (i) Metallized area is covered with resist and a n o t h e r mask is used to identify areas w h e r e metal is to be preserved. Wafer is etched to r e m o v e u n w a n t e d metal. Resist is then dissolved. 178 Chapter 6 Fabrication Technology / / / / / / / / / // -///777[ SiO, Ν + N substrate (a&b) (C) \ t I \ \ t t \ \ \ \ positive positive photoresist photoresist A' + + N N (d) (e) SiO, Ν V/////A K///////I ν Ρ 7 TV (f) (g) SiO, N+ N+ (h) (i&j) Figure 6.12 Typical steps in the fabrication of a planar PN junction diode. (j) Contact metal is deposited on t h e back surface and ohmic contacts are m a d e by heat treatment. In t h e following chapters, we will b e discussing o t h e r devices. W h e r e v e r appro­ priate and necessary, reference to the particular fabrication techniques will be illus­ trated. 6.6 F A B R I C A T I O N O F R E S I S T O R S A N D C A P A C I T O R S IN ICs Resistors In integrated circuits, resistors are usually m a d e of impurities that are diffused into a semiconductor, which is of opposite polarity. They are m a d e by and from t h e processes that are used to form devices. Figure 6.13(a) shows a resistor m a d e of a Ρ region diffused into an N-epitaxial layer and to t h e ends of which metallic contacts are made. The section of the resistor, as dictated by the diffusion, is very nearly rec­ tangular in shape, as shown in Fig. 6.13(b). T h e resistance of the layer is given by  179 (b) (c) Figure 6.13 Resistors in integrated circuits (a) cross-section, (b) rectangular dimensions, and (c) meander pattern. R = pL/Wd where ρ is the average resistivity of t h e layer in ohm-cm, d is its thickness, L is its length and W is its width. Resistances in monolithic circuits are defined by a term k n o w n as the sheet resistance. The sheet resistance has units of o h m s p e r square, it being the resistance of a square having W = L. Assuming 100 to 200 o h m s p e r square, practical resistors may have values ranging from 100 to several kilohms. H i g h e r resistances are obtained by using a m e a n d e r pattern, as shown in Fig. 6.11(c). T h e major p r o b l e m with resistors of high values is that they tend to occupy a large area on t h e chip. A resistor of 50 Kohms uses u p an area of the semiconductor that may b e occupied by h u n d r e d s of transis­ tors. Ion implantation can b e used, however, to generate lightly d o p e d regions suit­ able for precision high-value resistors. Capacitors O n e type of capacitor in monolithic circuits is m a d e by using the capacitance formed b e t w e e n t h e Ρ and Ν regions of a reverse-biased diode. Such a capacitance is shown in Fig. 6.14. These capacitors, just like resistors, are formed in the same diffusion processes that are used to form devices. A s we will see in a later chapter, bipolar transistors are m a d e of t h r e e regions in which either of t h e two P N junctions may b e used as capacitors, w h e r e b y the b r e a k d o w n voltage of t h e capacitor m a y vary considerably from o n e to the other. 180 Chapter 6 Fabrication Technology V/////////. 'V/////////////A 1 Ν Figure 6.14 A capacitor in a monolithic circuit. The disadvantage of junction capacitors is the d e p e n d e n c e of the capacitance on t h e voltage applied t o t h e junction. Capacitors that are voltage-independent can + be formed from metal insulator N semiconductor layers, as used in M O S struc­ tures. M e t a l oxide semiconductor junctions and devices are studied in Chapters 12 and 13. PROBLEMS A N D QUESTIONS 6.1 A silicon crystal is to be grown by the Czochralski process and is to have in the melt 15 3 an arsenic concentration of 5 Χ 10 atoms/cm. The segregation coefficient of arsenic in silicon is 0.3. Determine the initial arsenic concentration in the crystal. 6.2 A silicon crystal is to be grown by the Czochralski process and is to contain 5 Χ 10 15 3 boron atoms/cm. Given k for boron is 0.8: Q a) Determine the initial concentration of boron atoms in the melt to produce the required density. b) If the initial amount of silicon in the crucible is 50kg, how many grams of boron should be added? 6.3 A crystal of silicon is to be grown using the Czochralski process. The melt contains 10kg of silicon to which is added lmg of phosphorus. Given k (phosphorus) = 0.35, 0 atomic weight of silicon = 28.09, atomic weight of phosphorus = 30.97, and density of 3 phosphorus = 0.35g/cm , determine the initial dopant concentration in the solid at 22 -3 the beginning of the growth if the atomic density of silicon is 5 Χ 10 c m. 6.4 In the diffusion process, Q is defined as the total number of atoms per unit area of the semiconductor. where C(x,t) = C erfc [*/(2λ/Ζ)ί)] s Use the equation for the predeposition concentrations to determine an expression for Q in terms of D, t, and C. S 6.5 A certain process requires a boron predeposition diffusion step into an N-type wafer. 15 The wafer has been uniformly doped, prior to this step, by 1 Χ 10 phosphorus 3 atoms/cm. The predeposition step is carried out at 1000°C for 30 minutes. The diffu­ 14 2 sion coefficient, D, of boron in silicon at 1000°C is 1.78 X 10~ cm /s and the solid sol­ 20 3 ubility of both boron and phosphorus in silicon is assumed to be 3 X 10 /cm at the relevant temperature. Determine: a) The diffusion length for this step.  Chapter 6 Problems 181 b) The surface concentration C after this step. S 2 c) The number of boron atoms/cm , Q, after this step. Note that the dopant density cannot exceed the solid solubility in silicon. 6.6 The predeposition step of Problem 6.5 is followed by a drive-in diffusion step at 1050°C for 4 hours. Given the diffusion coefficient of boron in silicon at 1050°C is 17.3 14 3 X 10" cm /s, determine: a) The surface concentration after the drive-in step. b) Q after the drive-in step. c) The junction depth after the drive-in step, recalling that the phosphorus con­ 15 3 centration is 1 X 10 /cm. Note that since no new dopant is introduced during the drive-in step, the Q at the ini­ tiation of this step is the same as that at the completion of the predeposition step. 6.7 List the principal advantages and disadvantages of ion implantation. 6.8 Why are two diffusion steps normally used when one would be less costly? 6.9 What is the main reason for the use of epitaxy in the fabrication of microcircuits?