Semiconductor Manufacturing Process PDF

Semiconductor Manufacturing Process Introduction to Analog Circuits Design (EST 160) Prepared by: Engr. Rochelle M. Sabarillo Step-By-Step Fabrication Process: From Silicon Wafers to Functional Chips Fabrication...

Semiconductor Manufacturing Process Introduction to Analog Circuits Design (EST 160) Prepared by: Engr. Rochelle M. Sabarillo Step-By-Step Fabrication Process: From Silicon Wafers to Functional Chips Fabrication of semiconductor is a very crucial process. Fabrication is based on CMOS technology. CMOS transistors are fabricated on Si wafers. Why silicon? Because it is economical, provides better conductivity and less noise, and has ease of formatting the structure of the MOSFET transistor. Silicon is the base material for MOS fabrication. Department of Electrical Engineering & Technology 2 Semiconductor Manufacturing Process Department of Electrical Engineering & Technology 3 Semiconductor Manufacturing Process For more information about the semiconductor manufacturing process, let’s watch this video. Title: Semiconductor Manufacturing Process Link: https://youtu.be/Bu52CE55BN0?si=V_WVN14I1IBoau7b Department of Electrical Engineering & Technology 4 Wafer Manufacturing Wafer manufacturing is a crucial process in the semiconductor industry, where raw materials are processed to create thin, flat disks known as wafers. These wafers serve as the substrate for fabricating semiconductor devices like integrated circuits (ICs), sensors, and other microelectronic components. This process includes: 1. Raw Material Preparation (Si Ingot Production) 2. Ingot Slicing 3. Wafer Polishing 4. Wafer Cleaning Department of Electrical Engineering & Technology 5  Oxidation Oxidation is the process of making an oxide layer (SiO 2) or insulating layer into the wafer to control current flow, isolate the components, and improve device performance. For that, it uses an oxidation furnace at 900-1200 degree Celsius with H 2O or O2. Some of the important uses of SiO2 are as follows. - In bipolar and MOS transistors, it isolates one device from other. - It provides surface passivation. - It acts as a barrier or mask against the diffusion or the implantation of impurity dopant in substrate. - In MOS devices, it acts as a component. - It serves as a dielectric isolation between multilevel inter connect layers. Department of Electrical Engineering & Technology 6 Oxidation There are different techniques of forming a SiO2 layer. Thermal oxidation. This is the basic process used in IC fabrication. This technique is used when the charge density level at the interface of silicon and oxide is required low. Wet anodization Vapor phase oxidation. This process is also known as chemical vapor deposition. In multilevel structures, the SiO2 layer is formed on the top of the metal layer using the vapor phase oxidation process. Plasma oxidation Department of Electrical Engineering & Technology 7 Lithography Lithography is the process of transferring patterns of geometric shapes in a mask to a thin layer of radiation-sensitive material (called resist) covering the surface of a semiconductor wafer. Photolithography uses E-beam and includes various further steps such as, 1. Oxidation Layering 2. Photoresist Coating 3. Stepper Exposure 4. Development and Bake 5. Acid Etching 6. Spin, Rinse, and Dry Department of Electrical Engineering & Technology 8 Photomask Design A photomask is basically a “master template” of an IC design. A mask comes in different sizes. A common size is 6- x 6-inch. A basic and simple mask consists of a quartz or glass substrate. The photomask is coated with an opaque film. More complex masks use other materials. In the semiconductor process flow, a chipmaker first designs an IC, which is then translated into a file format. Then, in a photomask facility, a photomask is produced based on that format. The mask is a master template for an IC design. It replicates the original IC design. In a fab, the mask as well as a wafer are inserted in a lithography scanner. A photoresist, a light-sensitive material, is applied on the wafer. In operation, the scanner generates light, which is transported through a set of projection optics and the mask in the system. This process patterns the desired features on the wafer. Department of Electrical Engineering & Technology 9 Photomask Design Department of Electrical Engineering & Technology 10 Etching Etching is the process of removing unusual material from the wafer using chemicals or plasma. It is performed after lithography. Mainly two types of etching we used: 1. Wet Etching - a chemical process that involves the selective removal of material from a substrate using liquid etchants. These etchants are typically composed of a mixture of chemicals, such as acids, bases, or solvents, which react with the substrate material to form soluble products that can be easily washed away. 2. Dry Etching - a pivotal material removal technique, harnesses the potency of plasma —a highly reactive and energetic gas—for selective material removal from a substrate. Department of Electrical Engineering & Technology 11 Deposition Deposition is a process that deposits a blanket of materials on a surface. There are multiple ways to do this, including selective deposition, atomic-layer deposition, chemical vapor deposition and physical vapor deposition. Which technique is used depends upon the process node, the type of chip, and the amount of time needed to do the deposition. Conductive layers such as Poly-silicon and Aluminum, and insulation and protection layers such as Silicon Oxide ( SiO2 ) are deposited into the wafer surface by using Chemical Vapor Deposition ( CVD ) or Physical Vapor Deposition ( PVD ) in a high- temperature chamber. The deposition must be uniform throughout the wafer. Department of Electrical Engineering & Technology 12 Doping Ion implantation and diffusion are both techniques used to introduce dopants into semiconductor materials, but they differ significantly in their methods, precision, and applications. Here's a comparison of the two: Ion Implantation - Involves bombarding the semiconductor wafer with high- energy ions of the dopant element. The ions are accelerated in an electric field and directed towards the wafer. Applications: Used in advanced semiconductor devices (ICs) where precise doping is essential, such as in CMOS technology. Ideal for creating shallow doping profiles necessary for modern high-speed electronics. Diffusion - Involves placing the semiconductor wafer in a furnace with a dopant source, such as a gas or solid dopant, at high temperatures. The dopants diffuse into the semiconductor material over time. Applications: Used in older semiconductor technologies where precise control of doping profiles was less critical. Often used in conjunction with thermal oxidation processes to create doped regions in simpler devices. Department of Electrical Engineering & Technology 13 Diffusion vs. Ion Implantation Ion Implantation: Offers precise control of dopant concentration and depth, but can damage the semiconductor material and is more costly. Diffusion: A simpler and less expensive process but provides less control over the dopant profile and can result in more gradual doping profiles. In modern semiconductor manufacturing, ion implantation is preferred for its precision, especially in advanced technologies that require exact doping profiles. However, diffusion is still used in certain applications where its simpler and less damaging process is advantageous. Department of Electrical Engineering & Technology 1 4 Diffusion Diffusion is a method of adding impurities ( N-type or P-type ) into the silicon wafer to create regions for MOSFET transistors. For that, the wafer is placed in a furnace with relevant materials for N-well and P-well. The main aim of the Diffusion Process in IC Fabrication is to change the Conductivity of silicon substrate over a depth. The Diffusion Process in IC Fabrication is used in bipolar device technology to form bases, emitters, collectors ; while in MOS device technology to form source and drain region. The impurity or dopant can be added into silicon by using one of the most commonly used methods given below, 1. Diffusion from a chemical source at high temperatures, 2. Diffusion from doped oxide source, 3. Diffusion from an ion-implanted Department of Electrical Engineering & Technology 15 Ion Implantation Ion implantation involves integrating high impurity concentrations in the regions of the transistor. It is defined as the process by which impurity ions are accelerated to high velocity and physically lodged into the target material. It is a process by which energetic impurity atoms can be introduced into a single crystal substrate in order to change its electronic properties. Dopant atoms are vaporized , accelerated , and directed at silicon substrate. They enter the crystal lattice , collide with silicon atoms , and gradually loose energy , finally coming to rest at some depth within the lattice. What’s the difference between diffusion and ion implantation? In diffusion, particles are spread through random motion from higher concentration regions to regions of lower concentration. Ion implantation involves the bombardment of the substrate with ions, accelerating to higher velocities. Department of Electrical Engineering & Technology 16 Metal Wiring Metal wiring is a critical process in semiconductor manufacturing, used to create electrical connections between various components on a semiconductor wafer. These connections, or interconnections, allow different parts of an integrated circuit (IC) to communicate with each other and function as a complete electronic system. Metal wiring in semiconductor manufacturing involves depositing, patterning, and etching metal layers to create the electrical connections necessary for IC functionality. This process includes metal deposition techniques, lithography for patterning, etching to define the wiring, annealing to improve properties, and testing to ensure quality. The success of the metal wiring process is crucial for the performance and reliability of semiconductor devices. Department of Electrical Engineering & Technology 17 Wafer Dicing Wafer dicing, also called wafer sawing or wafer cutting, refers to the process whereby a silicon wafer is cut into individual components called die or chips. The process of wafer dicing enables manufacturers of integrated circuits (ICs) and other semiconductor devices to harvest many individual dice from a single wafer. Given the extremely small dimensions associated with the imprinted circuit traces on the wafer, the dicing process is one that requires high-quality, high- precision machinery and careful monitoring from skilled operators with the proper training and experience. Department of Electrical Engineering & Technology 18 IC Packaging IC packaging refers to the material that contains a semiconductor device. The package is a case that surrounds the circuit material to protect it from corrosion or physical damage and allow mounting of the electrical contacts connecting it to the printed circuit board (PCB). IC packaging is the last stage in the production of semiconductor devices. During this important stage, the semiconductor block gets covered in a package that protects the IC from potentially damaging external elements and the corrosive effects of age. Department of Electrical Engineering & Technology 19 Common IC Package Types There are various ways to categorize IC packaging designs based on formation. As such, there are two types of IC packages: the lead-frame type and the substrate type. Pin-grid array: These are for socketing. Lead-frame and dual-inline packages: These packages are for assemblies in which pins go through holes. Chip scale package: A chip scale package is a single-die, direct surface mountable package, with an area that’s smaller than 1.2 times the area of the die. Quad flat pack: A lead-frame package of the leadless variety. Quad flat no-lead: A tiny package, the size of a chip, used for surface mounting. Multichip package: Multichip packages, or multichip modules, integrate multiple ICs, discrete components and semiconductor dies onto a substrate, making it so the multichip package resembles a larger IC. Area array package: These packages offer maximum performance while still conserving space by allowing any portion of the chip’s surface area to be used for interconnection. Department of Electrical Engineering & Technology 20 Common IC Package Types Pin-grid array: Quad flat pack: Lead-frame and dual-in line Quad flat no-lead: package: Department of Electrical Engineering & Technology 21 Testing Finally, it's time to test the functionality of fabricated semiconductor chips. During the fabrication process, various rules and considerations must be followed such as, 1. Design Rule Check ( DRC ) 2. Scalable-Design Rule 3. Micron-Rules Process 4. Circuit-Under Test 5. Packaging ICs Rules 6. Cleanroom Environment, etc. Department of Electrical Engineering & Technology 22 Fabrication Process: Inverter VLSI Fabrication Process: https://www.youtube.com/watch?v=fwNkg1fsqBY The fabrication sequence consists of a series of steps in which layers of the chip are defined through a process called photolithography. The inverter could be defined by a hypothetical set of six masks: n-well, polysilicon, n+ diffusion, p+ diffusion, contacts, and metal. Masks specify where the components will be manufactured on the chip. Department of Electrical Engineering & Technology 23 Inverter Cross-Section Department of Electrical Engineering & Technology 24 Fabrication Process: Inverter Mask Set Department of Electrical Engineering & Technology 25 Fabrication Process: Inverter Mask Set Department of Electrical Engineering & Technology 26 Fabrication Process: Cross-sections while manufacturing the n-well Figure (a) illustrates the bare substrate before processing. The wafer is first oxidized in a high-temperature (typically 900–1200 °C) furnace that causes Si and to react and become Si on the wafer surface (Figure (b)). The oxide must be patterned to define the n-well. An organic photoresist that softens where exposed to light is spun onto the wafer (Figure (c)). The photoresist is exposed through the n-well mask that allows light to pass through only where the well should be. The softened photoresist is removed to expose the oxide (Figure (d)). The oxide is etched with hydrofluoric acid (HF) where it is not protected by the photoresist (Figure (e)), then the remaining photoresist is stripped away using a mixture of acids called piranha etch (Figure (f )). Department of Electrical Engineering & Technology 27 Fabrication Process: Cross-sections while manufacturing the n-well The well is formed where the substrate is not covered with oxide. Two ways to add dopants are diffusion and ion implantation. In the diffusion process, the wafer is placed in a furnace with a gas containing the dopants. When heated, dopant atoms diffuse into the substrate. Notice how the well is wider than the hole in the oxide on account of lateral diffusion (Figure (g)). With ion implantation, dopant ions are accelerated through an electric field and blasted into the substrate. In either method, the oxide layer prevents dopant atoms from entering the substrate where no well is intended. Finally, the remaining oxide is stripped with HF to leave the bare wafer with wells in the appropriate places. Department of Electrical Engineering & Technology 28 Fabrication Process: Cross-sections while manufacturing polysilicon and n-diffusion The transistor gates are formed next. These consist of polycrystalline silicon, generally called polysilicon, over a thin layer of oxide. The thin oxide is grown in a furnace. Then the wafer is placed in a reactor with silane gas (Si) and heated again to grow the polysilicon layer through a process called chemical vapor deposition. The polysilicon is heavily doped to form a reasonably good conductor. The resulting cross-section is shown in Figure (a). As before, the wafer is patterned with photoresist and the polysilicon mask, leaving the polysilicon gates atop the thin gate oxide (Figure (b)). The n+ regions are introduced for the transistor active area and the well contact. As with the well, a protective layer of oxide is formed (Figure (c)) and patterned with the n-diffusion mask to expose the areas where the dopants are needed (Figure (d)). Although the n+ regions in Figure (e) are typically formed with ion implantation, they were historically diffused and thus still are often called n-diffusion. Department of Electrical Engineering & Technology 29 Fabrication Process: Cross-sections while manufacturing polysilicon and n-diffusion Notice that the polysilicon gate over the nMOS transistor blocks the diffusion so the source and drain are separated by a channel under the gate. This is called a self-aligned process because the source and drain of the transistor are automatically formed adjacent to the gate without the need to precisely align the masks. Finally, the protective oxide is stripped (Figure (f )). Department of Electrical Engineering & Technology 3 0 Fabrication Process: Cross-sections while manufacturing p-diffusion, contacts, and metal The process is repeated for the p-diffusion mask to give the structure of Figure (a). Oxide is used for masking in the same way, and thus is not shown. The field oxide is grown to insulate the wafer from metal and patterned with the contact mask to leave contact cuts where metal should attach to diffusion or polysilicon (Figure (b)). Finally, aluminum is sputtered over the entire wafer, filling the contact cuts as well. Sputtering involves blasting aluminum into a vapor that evenly coats the wafer. The metal is patterned with the metal mask and plasma etched to remove metal everywhere except where wires should remain (Figure (c)). This completes the simple fabrication process. Department of Electrical Engineering & Technology 3 1 Layout Design Rules Layout design rules describe how small features can be and how closely they can be reliably packed in a particular manufacturing process. Industrial design rules are usually specified in microns. This makes migrating from one process to a more advanced process or a different foundry’s process difficult because not all rules scale in the same way. Mead and Conway popularized scalable design rules based on a single parameter, λ, that characterizes the resolution of the process. λ is generally half of the minimum drawn transistor channel length. This length is the distance between the source and drain of a transistor and is set by the minimum width of a polysilicon wire. For example, a 180 nm process has a minimum polysilicon width (and hence transistor length) of 0.18 µm and uses design rules with λ = 0.09 µm. Designers often describe a process by its feature size. Feature size refers to minimum transistor length, so λ is half the feature size. Department of Electrical Engineering & Technology 3 2 Layout Design Rules The MOSIS service is a low-cost prototyping service that collects designs from academic, commercial, and government customers and aggregates them onto one mask set to share overhead costs and generate production volumes sufficient to interest fabrication companies. MOSIS has developed a set of scalable lambda-based design rules that covers a wide range of manufacturing processes. The rules describe the minimum width to avoid breaks in a line, minimum spacing to avoid shorts between lines, and minimum overlap to ensure that two layers completely overlap. A conservative but easy-to-use set of design rules for layouts with two metal layers in an n-well process is as follows: - Metal and diffusion have minimum width and spacing of 4 λ. - Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and below. - Polysilicon uses a width of 2 λ. - Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a spacing of 1 λ away where no transistor is desired. - Polysilicon and contacts have a spacing of 3Department λ from other polysilicon of Electrical Engineeringor & contacts. Technology 33 - N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ. Layout Design Rules Figure below shows the basic MOSIS design rules for a process with two metal layers. Transistor dimensions are often specified by their Width/Length (W/L) ratio. Department of Electrical Engineering & Technology 3 4 Layout Design Rules: Inverter pMOS transistors are often wider than nMOS transistors because holes move more slowly than electrons so the transistor has to be wider to deliver the same current. Figure (a) shows a unit inverter layout with a unit nMOS transistor and a double-sized pMOS transistor. Figure (b) shows a schematic for the inverter annotated with Width/Length for each transistor. In digital systems, transistors are typically chosen to have the minimum possible length because short-channel transistors are faster, smaller, and consume less power. Figure (c) shows a shorthand we will often use, specifying multiples of unit width and assuming minimum length. Department of Electrical Engineering & Technology 3 5 Gate Layouts “Line of diffusion” rule is commonly used for standard cells in automated layout systems. This style consists of four horizontal strips: metal ground at the bottom of the cell, n-diffusion, p-diffusion, and metal power at the top. The power and ground lines are often called supply rails. Polysilicon lines run vertically to form transistor gates. Metal wires within the cell connect the transistors appropriately. Figure (a) shows such a layout for an inverter. Figure (b) shows the same inverter with well and substrate taps placed under the power and ground rails, respectively. Department of Electrical Engineering & Technology 3 6 Gate Layouts Figure here shows a 3-input NAND gate. Notice how the nMOS transistors are connected in series while the pMOS transistors are connected in parallel. Power and ground extend 2 λ on each side so if two gates were abutted the contents would be separated by 4 λ, satisfying design rules. The height of the cell is 36 λ, or 40 λ if the 4 λ space between the cell and another wire above it is counted. All these examples use transistors of width 4 λ. These cells were designed such that the gate connections are made from the top or bottom in polysilicon. In contemporary standard cells, polysilicon is generally not used as a routing layer so the cell must allow metal2 to metal1 and metal1 to polysilicon contacts to each gate. While this increases the size of the cell, it allows free access to all terminals on metal routing layers. Department of Electrical Engineering & Technology 37 Know More Here’s a list of videos that will increase your knowledge about MOSFETs and the semiconductor industry: Title: Chip Manufacturing - How are Microchips made? Link: https://www.youtube.com/watch?v=bor0qLifjz4 Title: Inside The Worlds Largest Semiconductor Factory Link: https://www.youtube.com/watch?v=Hb1WDxSoSec Department of Electrical Engineering & Technology 3 8 What to Learn Next . Department of Electrical Engineering & Technology Reminder Prepare for oral participation. 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