Unit 2.pdf

MARWADI UNIVERSITY Subject Code:01CE0509 Subject Name: Fundamental of Processors B.Tech. Year–III Unit- 2  Outline Looping Syllabus Unit-2 Introduction of 8086 Microprocessor 8086 Architecture BIU EU Pin Co...

MARWADI UNIVERSITY Subject Code:01CE0509 Subject Name: Fundamental of Processors B.Tech. Year–III Unit- 2  Outline Looping Syllabus Unit-2 Introduction of 8086 Microprocessor 8086 Architecture BIU EU Pin Configuration of 8086 Syllabus Unit-2 3 INTRODUCTION It is upgraded microprocessor from 8085, 8086 has following features  8086 has 16 bits ALU (8085 has 8 bits ALU). SO, Operating speed increased.  8086 has 16 bits of Data bus. So, in one machine cycle it can transfer 2 bytes.[8085 has 8 bits of data bus.]  8086 has 20 bits of Address bus. With 8086 we can interface 2^20 = 1 MB [8085 has 16 bits address bus.]  8086 has two internal hardware units.  BIU – Bus Interface Unit & EU- Execution Unit 4 INTRODUCTION It is upgraded microprocessor from 8085, 8086 has following features  8086 supports pipelining. So, Multiple instructions can be executed in parallel.  Four 16 bits general purpose registers [AX, BX, CX, & DX]. We can use it in 8 bits also [AH, AL, BH, BL, CH, CL, DH, DL].  Two 16 bits index registers [ SI and DI]  Two 16 bits stack pointers[SP and BP] 5 INTRODUCTION It is upgraded microprocessor from 8085, 8086 has following features  8086 supports memory segmentation 1. CS – Code Segment 2. DS – Data Segment 3. ES – Extra Segment 4. SS – Stack Segment 16 bit Flag Register.[8085 has 8 bit flag register] Two Hardware modes  Maximum Mode  Minimun Mode 6 INTRODUCTION It is upgraded microprocessor from 8085, 8086 has following features  8086 provided memory banks. So,1MB is bisected into two bank of 512KB,  Lower Bank [Even Memory Address]  Higher Bank[Odd Memory Address]  8086 had upgraded instructions set and interrupt service. 7 History of Microprocessor 8 8086 Architecture 8086 has two internal hardware units.  BIU :Bus Interface Unit  BIU controls the address, data and control buses.  Operations:  Instruction Fetching  Queuing  Operand fetch, Store & address relocation 9 8086 Architecture 8086 has two internal hardware units.  EU :Execution Unit  EU contains ALU, flags and general purpose registers.  Operations:  Arithmetic and Logical Operations. 10 8086 Architecture  Pipelining:It helps to execute multiple Instructions in parallel 8085 Instruction Execution F1 E1 F2 E2 F3 E3 8086 Instruction Execution F1 E1 F2 E2 F3 E3 11 8086 Architecture  Bus Interface Unit consists of following: 1. Instruction Queue: 8086 is consists of a FIFO(first in first out) 6 byte registers set arranged like pipe is called Instruction queue. BIU continuously perform fetch operations from the Memory while the processor is executing current operation. Pre-fetched bytes are stored in the queue and EU will read this bytes as and when it requires. 12 8086 Architecture  Bus Interface Unit consists of following: 2. Segment Register:  The memory of 8086 is of 1MB which is divided into four segments.  For that 8086 consists of four 16-bit segment register 1. CS – Code Segment 2. ES – Extra Segment 3. SS – Stack Segment 4. DS – Data Segment 13 8086 Architecture  Bus Interface Unit consists of following: 2. Segment Register: 1. CS – Code Segment  16 bit register  Stores the base address of 64 KB segment and microprocessor instructions.  Like any other segment register CS can not be changed directly.  During the execution of Far jump, Far call or Far return instruction, The CS register is automatically updated. 14 8086 Architecture  Bus Interface Unit consists of following: 2. Segment Register: 2. ES – Extra Segment  16 bit register  Which contain starting address of 64 KB segment.  Used to store data.  ES by default holds the destination location for the string data which are always pointed by the DI register.  We can not load it by immediate value.  It can be changed by POP and LES instructions. 15 8086 Architecture  Bus Interface Unit consists of following: 2. Segment Register: 3. SS – Stack Segment  16 bit register  Containing offset address of 64 KB segment.  Used as stack memory which operated as Last In First Out (LIFO).  Stack Pointer (SP) and Base Pointer(BP) are Pointer registers.  PUSH and POP are main Instructions.  We can not load it by immediate value.  It can be changed using POP instruction. 16 8086 Architecture  Bus Interface Unit consists of following: 2. Segment Register: 4. DS – Data Segment  16 bit register  Holds logical address of 64 KB data segment.  Used to store the data  AX, BX, CX, DX and index registers SI and DI are the by default registers of this segment.  We can not load it by immediate value.  It can be changed using POP and LDS instructions. 17 8086 Architecture  Bus Interface Unit consists of following: 3. Instruction Pointer and address summation:  CS contains Base address and IP contains of logical or offset address  How it will convert into 20 bit physical address?  The CS are shifted left by 4 bits. Lowest four bits filled with zeros. OR  CS register value multiply by decimal 16 or hexadecimal 10H.  Resulting value added with content of Instruction pointer to make 20 bit physical address.  PA = CS * 10H + IP 18 8086 Architecture  Bus Interface Unit consists of following: 3. Instruction Pointer and address summation: 15 0 Segment Segment Register Register 16 bit 0000 16 bit Offset vale 15 0 16 bit X 16 or x10H IP Adder Adder 20 bit Address 20 bit Address 19 8086 Architecture  Execution Unit consists of following: 1. Four 16-bit General Purpose Data Registers Which can be used as 8-bit data Register. 2. Four 16-bit pointers and base registers. 3. 16 bit Flag Register. 20 8086 Architecture  Execution Unit consists of following: 1. Four 16-bit General Purpose Data Registers:  8086 consists of four 16-bit Data registers AX, BX, CX and DX.  Each of these divided into two parts as Higher and Lower part to store 8-bit data.  These registers performs some specific functions.  AX is used as 16-bit accumulator as well as  AL is used as a 8-bit accumulator.  Accumulator used in multiplication, Division, shift and Rotate operations. 21 8086 Architecture  Execution Unit consists of following: 1. Four 16-bit General Purpose Data Registers:  16-bit Base Register BX can be used as memory pointer in Data segment.  Used as based, based indexed or register indirect addressing mode.  Counter Register (CX) or CL can be used as counter in string manipulation and Shift/ rotate instructions.  Used as Default counter in Loop instruction. 22 8086 Architecture  Execution Unit consists of following: 1. Four 16-bit General Purpose Data Registers:  Data Register DX is used in DIV instructions to hold the higher word of the 32-bit operand and the remainder after division.  It is used in Multiplication operation to hold the higher word of 32-bit result.  When the IO address is of 16-bit than DX register is, by default used hold the 16-bit IO address. 23 8086 Architecture  Execution Unit consists of following: 2. Four 16-bit Pointers and base Register:  These are SP, BP, SI and DI.  Used to hold offset or logical addresses within segments.  Stack Pointer(SP) is a 16-bit register pointing to program stack.  Base Pointer(BP) is a 16-bit register pointing to data in stack segment. 24 8086 Architecture  Execution Unit consists of following: 2. Four 16-bit Pointers and base Register:  Destination Index (DI) is a 16-bit Register.  Used as a destination data address in string manipulation instructions.  Source Index (SI) is a 16-bit register.  Used as a source data address in string manipulation instructions. 25 8086 Architecture  Execution Unit consists of following: 3. Flag Register:  8086 consists of one 16-bit Flag Register.  It is a set of 16 Independent Flipflops.  6 are status flag.  3 are control flag. And 7 flip flops are reserved. 26 8086 Architecture 3. Flag Register: a) Status Flags i. Carry Flag: This Flag is set when an arithmetic carry or borrow has been generated during addition and subtraction operation. 27 8086 Architecture 3. Flag Register: a) Status Flags ii. Parity Flag: Parity flag indicates the number of 1s are even or odd. If the number of 1s are even then it will be set. If odd then it will be clear. 28 8086 Architecture 3. Flag Register: a) Status Flags iii. Auxiliary Carry Flag: It shows carry propagation from D3 to D4 position. 29 8086 Architecture 3. Flag Register: a) Status Flags iv. Zero Flag: The Zero flag is indicates whether the result of a Mathematical or logical operation is zero or non-zero. For a zero result this result will be set, otherwise it will be clear. 30 8086 Architecture 3. Flag Register: a) Status Flags v. Sign Flag: This Flag indicates whether the result of mathematical operation is negative or positive. If positive then it will be clear. It represent the status of D7 bit. 31 8086 Architecture 3. Flag Register: a) Status Flags vi. Overflow Flag: This flag is used in signed arithmetic operation. If the signed result is of more bits than the destination operand, then it will be set. To understand better, consider the example. 32 8086 Architecture 3. Flag Register: b) Control Flags: i. Trap Flag (TF): If this flag is set, a single step interrupt occurs after the execution of the next instruction. It is used for single step debugging, and set or cleared by software. 33 8086 Architecture 3. Flag Register: b) Control Flags: ii. Interrupt Enable Flag (IF): This flag is used to mask or unmask the maskable interrupts. When this flag is set, maskable interrupt will excute. This flag is set or cleared by software. 34 8086 Architecture 3. Flag Register: b) Control Flags: iii. Direction Flag (DF): This flag is used to String related operations. It causes string instructions to auto decrement the appropriate index register (SI or DI) when set. If it is cleared, then the index registers will be in auto increment mode. 35 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 1. AD0-AD15(Address data bus): These lines are multiplexed address/data lines. During T1 state of machine cycle, these lines carry address and for the rest of the T states these lines carry the data. The A0 line along with BHE defines whether lower byte, higher byte or word. 36 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 2. A19 /S6, A18/S5, A17/S4, A16/S3(Address and status lines): These are the upper four address lines. These lines are multiplexed with the status signals S3, S4, S5, S6. During T1 state, these act as address lines for memory operation. During I/O operations these lines are low. 37 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 2. A19 /S6, A18/S5, A17/S4, A16/S3(Address and status lines): S3, S4 give information about the segment which currently used by the processor. S4 S3 Segment in use 0 0 Alternate or Extra Segment (ES) 0 1 Stack Segment(SS) 1 0 Code Segment(CS) or none 1 1 Data Segment (DS) S5 keeps the value of Interrupt Enable Flag. S6 is always low. 38 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 3. BHE¯ / S7 (bus high enable/ status): The BHE¯ signal is used to enable the higher or the odd memory bank. During T1 state, the bus high enable BHE¯ is used to enable data on to the D15-D8 data lines which are connected with odd memory bank. S7 signal used by 8087 numeric coprocessor to determine whether the CPU is 8086 or 8088. S7 is always low 39 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 3. BHE¯ / S7 (bus high enable/ status): The BHE¯ along with the A0 address lines is used to the even or the odd both the banks as shown in table. BHE¯ A0 Operation 0 0 Word (16 bit) will be access 0 1 Upper byte or odd byte will be access 1 0 Lower byte or even byte will be access 1 1 None 40 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 4. RD¯(read): It is an active low signal indicates memory or I/O read operation. 5. READY: This is an active high input signal. When a slower peripheral device is ready to receive / transmit the data, it will send READY signal to 8086. 41 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 6. INTR(interrupt request): It is an interrupt request signal. It is an active high level triggered input signal. 7. TEST¯: This is an active low input signal. During the wait state, 8086 continuously check this pin. If this input is low execution continuous. 42 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 8. NMI(non-maskable interrupt): NMI is the non maskable interrupt. This interrupt can not be masked or denied. 9. RESET: RESET causes the processor to immediately terminate its current operation. Active high for at least for 4 clock cycles. 43 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 10. CLK(clock): The CLK provides basic timing to the 8086. Input Signal and generated by the 8284 clock generator. 11. MN/MX¯(minimum/maximum): It Indicates the mode of processor. High indicates singe processor mode. Low indicates multiprocessor mode. 44 Pin Configuration of 8086  Pin Details of 8086: Common to Min and Max mode. 12. Vcc: This pin is connected with +5V power supply. 13. GND: It is a GROUND pin. Two ground pins for low power dissipation. 45 Pin Configuration of 8086  Pin Details of 8086: (Minimum Mode). MN/MX¯ = Vcc 1. HOLD (hold request): This pin is used by external devices like DMAC. When Hold activated microprocessor suspends current execution and stops using the buses. 2. HLDA (hold acknowledge): It indicates that the microprocessor has received the Hold request. It goes low after the Hold request is removed. 46 Pin Configuration of 8086  Pin Details of 8086: (Minimum Mode). MN/MX¯ = Vcc 3. WR ¯ : It is ACTIVE LOW OUTPUT signal. It indicates write operation either from memory or I/O. 4. M/IO ¯ It is a output signal. If High then Memory operation otherwise I/O operation. 47 Pin Configuration of 8086  Pin Details of 8086: (Minimum Mode). MN/MX¯ = Vcc 5. DT/R ¯ (data transmit/ receive): It is used to control the direction of data flow through the transceiver. If High then Data Transmitted If Low then Data receiving. 6. DEN¯(data enable) It is active low output signal. It is provided as an output enable for 8286/8287. 48 Pin Configuration of 8086  Pin Details of 8086: (Minimum Mode). MN/MX¯ = Vcc 7. ALE (address latch enable): It is an active high output signal. It is provided by the processor to latch the address. 8. INTA¯(interrupt acknowledge) It is active low output signal. Microprocessor sends this signal in response to an interrupt request signal. 49 Pin Configuration of 8086  Pin Details of 8086: (Maximum Mode). MN/MX¯ = GND 1. RQ0¯/GT0¯, RQ1¯/GT1¯(I/O REQUEST/ GRANT): It is same as HOLD and HLDA. This pins are used by other local bus masters to force the processor to release the local bus. Each pin is bidirectional. RQ0¯/GT0¯ has higher priority than RQ1¯/GT1¯ 50 Pin Configuration of 8086  Pin Details of 8086: (Maximum Mode). MN/MX¯ = GND 2. LOCK¯: It is active low output signal. If this signal is active, then the other bus masters will not allowed to take control over the system bus. Activated by LOCK instruction and remains active untill the completion of next instruction. The LOCK instructions is actually the prefix to an instruction. 51 Pin Configuration of 8086  Pin Details of 8086: (Maximum Mode). MN/MX¯ = GND 3. S2¯,S1¯,S0¯: These are three status output signals. applied to Bus controller 8288 to generate control signals and INTA. 52 Pin Configuration of 8086  Pin Details of 8086: (Maximum Mode). MN/MX¯ = GND 4. QS1, QS0 (queue status): It provides status to allow external tracking of the 8086 instruction queue. Interfaced with the status signals of the math coprocessor 8087 which tracks the queue of 8086. 53 Memory Organization of 8086 16) F0000H- FFFFFH The Memory is logically divided in code, stack, data and 15) E0000H- EFFFFH extra segments each of 64KB. 14) D000H- DFFFFH It can interface 1 MB memory = 1024KB=10,48,576 bytes 13)C0000H- CFFFFH 12) B0000H- BFFFFH Address range from 00000H to FFFFFH. 11)A0000H- AFFFFH 1MB / 64KB = 16 Segments 10) 90000H- 9FFFFH 2 Byte = 16 bits = 1 Word 9) 80000H- 8FFFFH Memory Data 8 ) 70000H- 7FFFFH 0FFFFH 1 byte 7 ) 60000H- 6FFFFH. 6 ) 50000H- 5FFFFH. 5 ) 40000H- 4FFFFH 64KB 00003H 1 byte 4 ) 30000H- 3FFFFH 00002H 1 byte 3 ) 20000H- 2FFFFH 00001H 1 byte 2 ) 10000H- 1FFFFH 00000H 1 byte WORD 1 ) 00000H – 0FFFFH 54 Memory Organization of 8086 Code Segment is separately defined. Stack segment is partially overlapped with Data and Extra Segment. Data and Extra Segments are Fully overlapped. The Code Segment always contain program or Instructions. The Stack Segment store data by PUSH, POP and CALL instructions. The Data and Extra Segments are used to store the data. 55 Memory Organization of 8086 Advantages of Memory Segmentation: a) We can Address 1 MB memory with 16 bit registers. b) Allow the Program to be more than 64KB by using more than one code, stack or data segment. c) We will have separate area for code data and stack information. d) We can relocate a program by simply changing the content of Code Segment register. e) Program can work on several data sets by reloading the DS registers. 56 Memory Organization of 8086  8086 can interface 1 MB memory which is 8 bit wide because most of the IO devices are 8 bit wide.  But our Microprocessor is a 16-bit microprocessor. The memory physically organized as an odd bank of 512 KB and Even bank of 512KB as shown in fig. Odd Memory bank having odd memory addresses Even memory bank having even memory addresses. Data on Even bank transferred in D0 to D7 data lines. Data on odd bank transferred in D8 to D15 data lines. 57 Memory Organization of 8086  BHE¯ is used to enable odd bank and A0 is used to enable even bank. BHE¯ A0 Operation 0 0 Word (16 bit) will be access 0 1 Upper byte or odd byte will be access 1 0 Lower byte or even byte will be access 1 1 None 58 Minimum mode and Maximum mode Configuration Minimum Mode Configuration of 8086  When the MN/MX¯ pin is connected with +5V. Processor operates in Minimum Mode.  Minimum mode configuration of 8086 consists of 1. Three 8 bit latches (IC 8282) 2. Two 8 bit transceivers (IC 8286) 3. One control signal generator 4. One clock Generator Latches are used to separate AD0-AD15, A16/S3 to A19/S6 and BHE¯/s7 signals. 59 Minimum mode and Maximum mode Configuration Minimum Mode Configuration of 8086  Latches are used to demultiplex the multiplexed lines AD0 to AD15, A16/S3 to A19/S6 and BHE¯/S7 signals.  The ALE controls the D-FF latches.  The Transceivers are used to Separate Data bus.  The control signal generator is used to generate IOR¯, IOW¯, MEMR¯ and MEMW¯.  Clock generator generates the required clock frequency and Synchronize the READY and RESET signals. 60 Minimum mode and Maximum mode Configuration Maximum Mode Configuration of 8086  When the MN/MX¯ pin is connected with 0V. Processor operates in Maximum Mode.  More than one processor like coprocessor 8087 or independent 8086 or 8088 is interfaced in this mode.  Maximum mode configuration of 8086 consists of 1. Three 8 bit latches (IC 8282) 2. Two 8 bit transceivers (IC 8286) 3. One clock Generator (8284) 4. Bus Controller (8288) 5. Interrupt controller (8259) 61 Minimum mode and Maximum mode Configuration Maximum Mode Configuration of 8086  Bus controller 8288 generates the control signals. 62 Bus Cycle of 8086  Instruction Cycle is defined as Time taken by the processor to execute the Instruction.  Typically all the processors utilizes the following Five steps: 1. Step 1: Fetch the Instruction from the main Memory: Processor loads the content of the Instruction Pointer (IP) on the address bus. Then processor generates the MEMR control signal. On receiving the control signal memory loads the opcode on the data bus. Which is placed in to Instruction Register. 2. Step 2: Decode the Instruction: The Instruction Decoder will Decodes what is to be done in response of an opcode. 3. Step 3: Fetch main data from Memory: Read Required data from the main memory. 4. Step 4: Execute the Instruction: Instruction decoder sends the decoded information to control unit who sends this data to relevant functional unit to perform the operation. 5. Step 5: Store Results: This result obtained by the execution of operation stores at destination location. 63 Bus Cycle of 8086 64 Bus Cycle of 8086  Memory Read Operation in Minimum Mode: 65 Bus Cycle of 8086  Memory Write Operation in Minimum Mode: 66 Bus Cycle of 8086  Memory Read Operation in Maximum Mode: 67 Bus Cycle of 8086  Memory Write Operation in Maximum Mode: 68 Thank You