4CS015 Week 5 Sequential Logic and Memory Lecture Notes PDF

4CS015 Lecture 5: Sequential Logic and Memory Prepared by: Uttam Acharya 1 The story so far We’ve looked Number System. We’ve learned conversion of Number System. We’ve looked at combinational logic circui...

4CS015 Lecture 5: Sequential Logic and Memory Prepared by: Uttam Acharya 1 The story so far We’ve looked Number System. We’ve learned conversion of Number System. We’ve looked at combinational logic circuits. We’ve designed an ALU from logic gates. 2 This week we will look at: Sequential Logic Pulses and clocks Timing Diagram Race Hazard Flip-Flop 3 The next step An ALU without any way of running a programme or storing information is just a calculator What we are going to looked at now, is how logic circuits work with time and what the implications are. 4 Combinational vs. Sequential Combinational Logic The output of the logic circuit is a function of the inputs Think ‘OR’ gate Sequential Logic The output of the circuit is a function of the current inputs and the previous output state To accomplish this, the circuit needs to remember what the previous state was i.e. It needs memory! 5 Sequential logic Creation of memory from Logic. By looking at the output of the last logic state. Modifying new logic state based on what went on before. Fig: block diagram of sequential circuit 6 Timing Diagram To show what goes on in a logic circuit over time, we use Timing Diagrams A Timing diagram is a Picture of the effect of a Wave Form, passing through a Logic Gate. The changes of a logic input signal with respect to time. 7 Timing Example – A Pulse The signal level is at a logical 0 before the pulse. It then rises to a logical 1 at the rising edge. It stays at a logical 1 for a period of time (the pulse duration). It then falls back to a logical 0 the falling edge. 8 A Clock A clock has a repeating wave form (or pulse). The period of a clock is measured from one rising edge to the next rising edge. The frequency of the clock is the number of complete periods in a Second. (Hz). The pulses of a CPU clock control its operation. i.e. A Clock Synchronises Operations in CPU. 9 Nanoseconds The timing diagrams show time to any level. If the clock waveform on the previous slide was for an Intel Pentium 3.2, the diagram would show 1.56 X 10-9 seconds (1.56 nanoseconds) A typical TTL logic gate takes up to 4 Nanoseconds to go from 0 to 1. 10 Timing Diagram for AND Gate 11 Timing Diagram for HALF ADDER 12 Timing Diagram for FULL ADDER 13 Race Hazard A race hazard occurs when an unintended spike (very short pulse ~4 to 10 nano seconds) causes an unexpected and undesired change of output to occur A B O/P Output should always theoretically be 0 A B (Boole’s Law), but transition time can cause a spike 14 An Interesting Circuit What do you think this circuit does? NOR Truth Table A B O/P 0 0 1 0 1 0 1 0 0 1 1 0 15 An Interesting Circuit NOR Truth Table 1 0 0 ? 1 1 0 ? A B O/P 0 0 1 0 1 0 0 ?1 0 ? 1 1 0 1 0 0 1 1 0 13 Simple Memory Block Initially Set and Reset are at Logic 0 Output at this point are not known. Putting a pulse on the Set input causes the Q output to become 1. Putting a pulse on the Reset causes the Q output to become 0. At rest, both inputs 0, the circuit remains in the same state. It remembers what happened last. 17 Timing For R-S Flip-Flop Any pulse on the SET input will ensure that the Q output is at a logic '1’. Any Pulse on the RESET input will ensure that the Q output is at a logic '0‘. 18 R-S Flip-Flop Truth Table Applying a pulse to both ‘Set’ and ‘Reset’ should never occur. S R Q Q Therefore, this is not defined in the truth table 0 0 Q Q 1 0 1 0 Note: n = time, n + 1 = time plus 1 (i.e. 0 1 0 1 ‘Next’) 1 1 X X 19 More Practical Memory The R-S Flip-Flop does not offer a very practical memory. It changes whenever the R or the S input is pulsed. In a larger circuit, we need to synchronize the changes on the output. 20 Clocked R-S Flip-Flop Changes are synchronized by the clock signal. R or S signal will only move to the flip flop when the clock pulse is high. 21 Memory Input Having 2 separate lines, Set and Reset, to store 1 bit of memory is inconvenient. Touse the memory on a CPU data bus, we much rather use one input to store the 1 bit. 22 D-type Flip-Flop Input D is transferred to output Q. If D (for data) is 1, what gets stored at Q? And if D is 0? 23 D-type Flip-Flop (rising edge clock) Clock C transfers data D to Q Timing Diagram on the rising edge of pulse. 24 D-type Flip-Flop (falling edge clock) inverter Clock C transfers data D to Q Timing Diagram on the falling edge of pulse. 25 More about different kind of memory in workshop… 26 Summary Timing diagrams, pulses and clocks Logic feedback, simple memory, RS Flip-flops Clocked memory, D-type Flip-flops 27 Thank you… 28