Sequential Logic and Memory - 4CS015

Course Information

• Course code: 4CS015
• Lecture topic: Sequential Logic and Memory
• Presenter: Uttam Acharya

Lecture Content Summary

• Previous topics covered number systems, number system conversions, combinational logic, and ALU design.
• This week's lecture focuses on sequential logic, pulses, clocks, timing diagrams, race hazards, and flip-flops.
• The discussion on sequential logic aims to analyze how logic circuits function with time and the resulting effects.

Sequential Logic vs Combinational Logic

• Combinational logic circuits' output depends solely on the current input.
• Sequential logic circuits' output depends on both current input and prior output states; hence, they require memory.

Sequential Logic Description

• Sequential logic involves the creation of memory from logic elements
• It involves looking at the last logic state's output
• It involves adapting new logic states based on prior events

Timing Diagrams

• These depict the behavior of logic circuits over time.
• They illustrate the changes of logic input signals with respect to time.
• They present a visual representation of how a waveform affects a logic gate.

Timing Example - A Pulse

• A pulse starts at a logical 0.
• The pulse rises to a logical 1 at the rising edge.
• It remains at 1 for a duration (pulse duration).
• It falls back to a logical 0 at the falling edge.

A Clock

• A clock generates repeating waveforms (pulses).
• The period is the time duration between two successive rising edges.
• Frequency is the number of complete periods per second (measured in Hz).
• The clock synchronizes operations in a CPU.

Nanoseconds

• Timing diagrams can show time to a nanosecond level.
• A typical TTL logic gate takes about 4 nanoseconds to transition from 0 to 1.

Race Hazard

• An unintended or unexpected spike (4-10 nanoseconds) arising from the time taken for circuit transitions can alter the output, which should theoretically be 0 (per Boolean logic).

Simple Memory Block

• Initially, Set and Reset inputs are at logic 0.
• A pulse on the Set input makes the Q output 1.
• A pulse on the Reset input makes the Q output 0.
• When both inputs are 0, the circuit retains the previous state (remembers).

R-S Flip-Flop

• Applying a pulse to both Set and Reset is invalid and undefined.
• The R-S flip-flop does not offer practical memory because it changes whenever either R or S is pulsed.
• Often, the circuit is part of a larger circuit, requiring output changes to be synchronized.

Clocked R-S Flip-Flop

• Changes only occur when the clock signal is high.

Memory Input

• Using separate Set and Reset lines for a single bit of memory is inefficient.
• A CPU data bus often uses a single input line to store a bit.

D-type Flip-Flop

• Data input (D) is transferred to the output Q upon clock signal change.

D-type Flip-Flop (rising edge clock)

• Transfer occurs when the clock pulse rises (changes state from low to high).

D-type Flip-Flop (falling edge clock)

• Transfer occurs when the clock pulse falls (changes state from high to low).

Further Discussion

• The notes will elaborate on other memory types in a workshop.