Digital Logic Sequential Circuits PDF
Document Details
Uploaded by Deleted User
Tags
Summary
This document provides a detailed explanation of sequential logic circuits, including various types of flip-flops (RS, D, JK, T) and their logic diagrams. The document also discusses different types of registers and shift registers. It is suitable for undergraduate-level study in computer science and/or electrical engineering.
Full Transcript
## Circuits Séquentiels: - Introduction: - Circuits with memory. - Output at a time "t" depends on the inputs and the previous state of the outputs. - They have complementary outputs. ### Les bascules asynchromes: - **Bascule RS** - **S=1** and **R=0**: Q=1. The flip-flop sets....
## Circuits Séquentiels: - Introduction: - Circuits with memory. - Output at a time "t" depends on the inputs and the previous state of the outputs. - They have complementary outputs. ### Les bascules asynchromes: - **Bascule RS** - **S=1** and **R=0**: Q=1. The flip-flop sets. - **R=1** and **S=0**: Q=0. The flip-flop resets. - **S=R=0**: Q=Q'. The flip-flop memorizes. - **S=R=1**: Forbidden state. It is not logically possible. #### TV: - **R** **S** **Q** **Q+** - 0 0 0 0 (Memorization) - 0 1 0 1 (Set) - 1 0 1 0 (Reset) - 1 1 X X (Forbidden state) #### **Logigramme:** - **R** and **S** are the inputs connected to a NAND gate with **Q**. - **S** connects to a NOT gate where it is connected to the other input of the NAND gate. - The output of the NAND gate is connected to **Q**. ### C.S asynchrones: - Outputs change state when there is a change in the inputs. ### C.S synchrones: - Outputs change state after receiving authorization signal. ### Bascules: - They are logic elements used for memorizing information. - They typically use one or two inputs. - **Bascule D:** - **D=1**: Sets the flip-flop. - **D=0**: Resets the flip-flop. - **D=Q**: It memorizes the output. #### TV: - **D** **Q** **Q+** - 0 0 0 - 1 0 1 - 1 1 0 #### **Logigramme:** - The input **D** goes to a NAND gate with **Q** and **Q** connected together to the other input. - The output of the NAND gate is connected to **Q**. #### Equation:** - D= S.D, R=D. - **Q=Q+D** - **Bascule JK:** - **J=K=1**: The flip-flop toggles. - **J=K=0**: The flip-flop memorizes. - **J=1, K=0**: The flip-flop sets. - **J=0, K=1**: The flip-flop resets. - **J=K=1**: Forbidden state - **Bascule T:** - **T=0**: The flip-flop memorizes - **T=1**: The flip-flop toggles #### Equation: - **Q=JQ+KQ** - **Q=TQ** - **The Flip-Flop** Clock Signal: - **H=1**: The flip-flop memorizes. - **H=0**: The flip-flop operates normally. - **H=1**: Front of the clock signal - **H=0**: Back of the clock signal #### **Functioning:** - There are three types of clock signals: - 1: Memorization - 0: Memorization - 1: Toggles - 0: Memorization - **The Flip-Flop** Clock Signal: - **Clock level high**: Sets the output to the last state - **Clock level low**: The flip-flop memorizes. - **Clock level high**: The flip-flop functions normally #### **Synchronization on low level:** - It's the opposite: - **H=1**: The flip-flop memorizes. - **H=0**: The flip-flop functions normally. #### **Synchronization on front:** - **front-rising**: The flip-flop memorizes. - **front-falling**: The flip-flop operates normally. ### Bascule JK Master-Slave: - It uses two flip-flops: _Master_ and _Slave_. - **Master** flip-flop memorizes the output. - **Slave** flip-flop executes the command given by _Master_. #### **Symbol:** - The symbol for a _Master-Slave_ flip-flop is a standard flip-flop with inputs for clock, J, and K. - The clock input is indicated by a small circle around it. #### **Diagram of states:** - The state diagram shows the possible transitions between states for the flip-flop. - The flip-flop has four states: - **00**: The flip-flop is in the reset state. - **01**: The flip-flop is in the set state. - **10**: The flip-flop is in the hold state. - **11**: The flip-flop is in the toggle state. #### **Front rising:** - The outputs of the flip-flop change only on the rising edge of the clock. - This minimizes the risk of race conditions, where the inputs change while the clock signal is high, and the resulting state of the flip-flop becomes unpredictable. #### **Front falling:** - The outputs of the flip-flop change only on the falling edge. ### **Registers:** - A register is a group of memory cells that can store binary information. - The number of bits in a register determines the number of memory cells. - The register can be implemented by using a series of flip-flops. #### **Types of registers:** - **Parallel-in, Parallel-out (PIPO):** This register has parallel inputs and outputs. - **Parallel-in, Serial-out (PISO):** This register takes in parallel data but outputs in series. - **Serial-in, Parallel-out (SIPO):** This register takes serial data, but outputs parallel. - **Serial-in, Serial-out (SISO):** This register has both serial input and output. #### **Register of memorization:** - Registers with parallel inputs and outputs, where inputs are passed into the output on the first positive edge of the clock. #### **Shift Registers:** - These register are a set of flip-flops connected in a way where each flip-flop can shift data to the next flip-flop. - Depending on how the flip-flops are connected, a transfer of data can happen to the right or the left. - Shift registers can be used for: - *Data storage* - *Shifting data* - *Performing arithmetic operations* - *Serial-to-parallel conversion* - *Parallel-to-serial conversion* #### **Clocked Shift Registers:** - Shift registers with a clock signal so that the output of each flip-flop is shifted to the next flip-flop on the active clock edge. #### **Shift registers to the right:** - This configuration has the serial data input on the left side of the shift register and is passed to the right. - The rightmost flip-flop has the serial data output. #### **Shift registers to the left:** - Shift registers that can take in serial data on the right side and pass it to the left. #### **Circular Shift Registers:** - This configuration connects the output of the rightmost flip-flop to the input of the leftmost flip-flop. - It creates a circular chain of data that can be shifted around. #### **Chronogram of a shift register** - The shift register moves one step to the right when the clock pulse is applied. ### **Counters:** - A counter is a type of digital circuit that can count events such as input pulses. - Counter output increases with each count. - The output of a counter is often used as an address for a memory location. #### **Types of Counters:** - **Synchronous counters:** - A counter where all flip-flops have a common clock. - The output of one flip-flop can be used to clock other flip-flops instead of a single clock. - **Asynchronous counters:** - A counter where flip-flops are clocked by the output of the previous flip-flop. - The output of the previous flip-flop serves as the clock for the next flip-flop. #### **Characteristics of counters:** - The number of states of a counter is determined by the number of flip-flops used in its design. - For counter with N bits, there are 2^N states. - If a counter reaches its maximum state, it will either reset to its initial state or will continue counting by wrapping around to its initial state. #### **Clocking counter:** - The counting process is done using the clock signal. - There may be counters with different responses depending on the rising or falling edges of the clock. - **For example**, the counter can be designed to count only on the rising edge of the clock and not the falling edge. #### **Types of Counters:** - **Up counters:** - The output of the counter increases with each clock pulse. - **Down counters:** - The output of the counter decreases with each clock pulse. #### **Examples of using Counters in circuit design:** - **Measurement** - **Control** - **Timing** - **The synchronous counter** is more commonly used in modern digital systems over the asynchronous counter because it is considered more accurate, predictable, and easier to control. #### **The problem of synchronization in counter** - Care must be taken to avoid problems with *timing* when designing a *synchronous counter*. - The *timing* of the clock pulses must be carefully considered to ensure that all flip-flops are clocked at the same time, or else the counter's output could be inaccurate.