Questions and Answers
In a two-address Instruction Set Architecture (ISA), such as Intel or Motorola, the expression Z = X * Y + W * U would typically be represented as:
LOAD R1, X MULT R1, Y LOAD R2, W MULT R2, U ADD R1, R2 STORE Z, R1
In a one-address ISA like MARIE, the expression Z = X * Y + W * U would be represented as:
LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z
In a stack-based ISA, the postfix expression Z = X * Y + W * U would be represented as:
PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD POP Z
Which of the following statements about instruction formats is correct?
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Given a system with 16 registers and 4K of memory, how many bits are required to address a register and a memory location, respectively?
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In a three-address ISA, the expression Z = X * Y + W * U would typically be represented as:
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Which of the following statements is true about the expression Z = X * Y + W * U in a stack-based ISA versus a three-address ISA?
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