Wafer Preparation Chapter 3 PDF

Chapter 3 Wafer Preparation  Contents  Semiconductor Basics Crystal Structure Crystal Defects  Wafer Manufacturing From Sand to Silicon Crystal Growth  Czochralski Growth  Float Zone Growth Wafer Preparation Semiconductor Basics Semiconductor has a conductiv...

Chapter 3 Wafer Preparation  Contents  Semiconductor Basics Crystal Structure Crystal Defects  Wafer Manufacturing From Sand to Silicon Crystal Growth  Czochralski Growth  Float Zone Growth Wafer Preparation Semiconductor Basics Semiconductor has a conductivity between conductors (metals like copper, aluminum) and insulators (rubber, wood). Most commonly used semiconductors are silicon (Si) and Germanium (Ge). They are group IV elements in the periodic table. So there are 4 electrons in the outermost shell. In a crystal structure of Si, every atom is covalently bonded to 4 atoms and shares a pair of electron with each of them. Figure 3.1 Silicon chemical symbol Figure 3.2 Simplified crystal lattice of Si Semiconductor Basics When an electron in the outermost shell leaves the atom, it becomes a free electron and can conduct electric current. At the same time, the “hole” created at the site where the electron leaves, allows other electron to “jump in” from other lattice site, resulting in a net flow of electron or conduction of electric current. Therefore, there are 2 types of current carriers, the electron carrier and the hole carrier. The higher the density of carriers, the higher the conductivity. Semiconductor’s conductivity can be controlled by adding certain impurities, called dopant. This process is called doping.  Semiconductor Basics B is a group III element, having 3 or 1 electron less than Si, it provides hole carriers to the Si lattice which is called acceptor. P & As are group V elements, with an extra electron in the outermost shell than Si thus provides extra electron carriers. Hence, they are Figure 3.3 Phosphorus and called donors. Boron doped Silicon lattice Type Dopant Group P-type Boron (B) III N-type Phosphorus (P), Arsenic (As) V Semiconductor Basics Generally, the higher the dopant concentration (/cm3) the higher the conductivity or 14 the lower the resistivity. 4.5 Given a dopant concentration of 1x1015/cm3, resistivity of n-type Silicon= 4.5 ohmcm Given the same dopant concentration of 1x1015/cm3, resistivity of p-type Silicon= 14 ohmcm N-type silicon has lower Dopant conc = 1015 resistivity than p-type silicon at the same dopant Figure 3.4 Plot of Resistivity vs Dopant concentration as electrons Concentration in Si move faster than holes Semiconductor Basics The electron & hole carriers from the an undoped Si lattice are called intrinsic carriers. The electron & hole carriers from the donors & acceptors respectively are called extrinsic carriers. Figure 3.5 Plot of Conductivity vs Temp Crystal Structure Wafer Substrate Single crystal silicon wafers are the most common material used in IC wafer fabrication. Process characteristics could depend on the crystalline perfection in the wafers. The material used can be divided into 3 classifications: o Single Crystal (monocrystalline) o Polycrystalline o Amorphous Crystal Structure Wafer Substrate Single Crystal (Monocrystalline) Almost all of the atoms in the crystal occupy well defined and regular position (lattice sites) Most of semiconductor substrates in which active devices are made are usually single crystal (Si wafer) Figure 3.6 Monocrystal (2D) Crystal Structure Wafer Substrate Polycrystalline The materials are a collection of small single crystals or grains randomly oriented with respect to each other. The size and orientation of these grains often change during processing and sometimes even during circuit operation. Figure 3.7 Polycrystal Crystal Structure Wafer Substrate Amorphous The atoms have no long range order. Figure 3.8 Amorphous Crystal Structure Crystals are described by their most basic structural element: unit cell. A crystal is simply an array of these cells, repeated in a regular manner over 3 dimension. The unit cells have cubic symmetry with each edge of the unit cell being the same length. Figure 3.9 Unit cell Crystal Structure wafer normally breaks at right angles of 90o. Typically 4 quadrants. wafer normally breaks at 60o. Typically, 6 pieces. orientation has a higher atom surface density. Therefore, it is stronger and is a better choice for higher-power devices. Si (100) plane Si (110) plane Si (111) plane Figure 3.10 Crystal structure of & wafers Crystal Structure and planes are the most popular orientations of single-crystal wafers for wafer fabrication. wafer is commonly used in MOS IC chip fabrication. wafer is commonly used for bipolar transistors and other IC chips. Basic lattice cell Basic lattice cell (a) (b) Figure 3.11 Lattice structure of and wafers Crystal Defects Although silicon wafers used for IC fabrication are highly perfect single crystals, they have defects/imperfections. Crystal defects or imperfections can be divided into four types: Point defects (do not extend in any direction) Line defects (extend in one direction through the crystal) Area defects (2-D defects) Volume defects (3-D defects) D Figure 3.12 Simple point & line defects: B (a) vacancies; Frenkel defect due to A (b) self-interstitials; } thermal excitation (c) substitutional impurities; C (d) edge dislocations; Agglomeration of point (e) dislocation loops } defects due to mechanical stress E Goto Pg 21 Crystal Defects 1. Point Defect A vacancy is a point defect where an atom is missing at a lattice site. An interstitial is a point defect where an atom resides between lattice site. If the interstitial atom is of the same material as the atoms in the lattice, it is a self-interstitial defect. The interstitial atom could come from a nearby vacancy. This vacancy interstitial combination is called a Frenkel Defect. Both vacancies and interstitials can move through the crystals, particularly under high temperatures typically found during processing conditions. They might also migrate to the surface of the wafer where it is annihilated. Vacancies and self-interstitials are intrinsic defects. Thermal excitation creates a very small percentage of electrons and holes in a semiconductor. Thermal excitation will also remove a small number of atoms from their lattice sites, leaving behind vacancies. Crystal Defects 1. Point Defect Figure 3.13 Number of Vacancy concentration is given by atoms in crystal lattice Nov = No e −Ea / kT /cm 3 ----- (3.1) where, No is the number density of atoms in the crystal lattice Ea is the activation energy associated with the formation of vacancy k is the Boltzman constant (8.617 x 10-5 eV/K) T is temperature (K) For Si, No = 5.02 x 1022 /cm3 Ea = 2.6 eV (electron Volts) Example: Calculate the vacancy concentration in Silicon at 784deg C. −𝐸𝐸𝐸𝐸 2.6 − −5 𝑁𝑁𝑣𝑣 = 𝑁𝑁𝑜𝑜 𝑒𝑒 𝑘𝑘𝑘𝑘 = 5.02𝑥𝑥1022 𝑒𝑒 8.617𝑥𝑥10 (784+273) = 2x1010 /cm-3 Crystal Defects 2. Line Defects Dislocations are geometric faults of the lattice. It can be an extra line (or plane) of atoms inserted between two lines (or planes) of atoms. Formed during wafer processing, dislocation is mainly associated with mechanical stress such as uneven heating/cooling, non-uniform film deposition. The bonds just before the insertion of Figure 3.14 the extra plane are stretched, the bonds just after Types of the plane are compressed dislocations Can also be a result of point defects moving randomly through the crystal come/ stick together until a dislocation or other higher dimensionality defects results – an effect called agglomeration edge dislocations Edge dislocation is the simplest type of dislocation. The extra plane (or line) is terminated on one end by the edge of the crystal. If the extra plane (or line) is completed and contained in the crystal, the defect is referred to as a dislocation loop. dislocation loops Crystal Defects 3. Area Defect The most obvious type of 2-D or area defect is polycrystalline grain boundary. Stacking fault is an extra plane of atoms in the lattice, similar to dislocation, but the pattern is disrupted in 2 dimensions and is regular in the third. Figure 3.15 Type I 90° partial dislocation cores (cyan atoms); yellow atoms represent stacking fault. Red atoms are on the first and third planes from the front while black atoms are on the second and forth planes. 4. Volume Defect 3-D or bulk defects are irregular in all 3 dimensions. A common example is a precipitate. Crystal Defects Defects are undesirable in active regions, where the transistors are located. However, defects in inactive regions have a beneficial effect as gettering sites. Gettering is a process by which impurities and defects diffuse through the crystal, and become trapped at the gettering sites. Intrinsic gettering In the process of single crystal silicon growth for wafer, there is always some oxygen being dissolved in the silicon crystal. Intrinsic gettering uses oxygen precipitates in the wafer as gettering sites. Point defect and residual impurities such as heavy metals are trapped at the precipitate sites away from the active regions. ACTIVE REGION Silicon substrate INACTIVE REGION Crystal Defects Intrinsic Gettering Typical oxygen concentrations in Si wafers are 10 to 40 ppm (ppm: parts per million, ~ 1018 /cm3). In order to use an intrinsic gettering process, the wafer should have a concentration of ~15ppm. If the concentration is smaller than that, the impurities are too far apart to agglomerate. Large concentrations will precipitate, but they will also lead to wafer warpage, and other extended defects, which may thread through the active regions. Crystal Defects Intrinsic Gettering The solid solubility of oxygen in Si is given by: 1.032 − Cox = 2 x 10 e 21 kT / cm3 ----- (3.2) where, k is the Boltzman constant (8.617 x 10-5 eV/K) T is the temperature (K) Example: Calculate the oxygen concentration in Silicon at room temp. 1.032 − 1.032 − 8.617 x 10−5 ( 300 ) C = 2 x 10 21 e kT = 2 x 10 21 e = 9.92 x103 / cm 3 ox Example: Convert concentration to ppm (parts per million)? Hint: 𝐶𝐶𝑜𝑜𝑜𝑜 x1 million 𝑁𝑁𝑜𝑜 9.92𝑥𝑥103 𝐶𝐶𝑜𝑜𝑜𝑜 (𝑝𝑝𝑝𝑝𝑝𝑝) = x 1000000 = 1.98x10-13 ppm 5.02𝑥𝑥1022 Crystal Defects Intrinsic Gettering A typical intrinsic gettering process consists of three steps: 1. Outdiffusion Denuded zone 2. Nucleation Silicon substrate 3. Precipitation The purpose of outdiffusion is to reduce the concentration of dissolved oxygen in a denuded zone (defect free zone) near the surface of the wafer where the active devices will be build. It is common to use denuded zone widths of two or three times the required junction depth. The zone is formed by annealing the wafer at high temperature in an inert ambient. The temperature must be high enough to allow oxygen to diffuse out of the surface, but low enough to reduce the concentration of oxygen to not less than 15ppm. Crystal Defects Denuded zone Ld Silicon substrate Intrinsic Gettering The width of the denuded zone in silicon can be approximated by: 1.2 − Ld = 0.091 t e kT cm ------ (3.3) where, t is the annealing time (s) k is the Boltzman constant (8.617 x 10-5 eV/K) T is the temperature (K) Using eq 3.2 and eq 3.3, the process time & temperature can be calculated. Example: Calculate the width of denuded zone created at 527 deg C over a time duration of 10mins. 𝟏𝟏.𝟐𝟐 − 𝑳𝑳𝒅𝒅 = 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎(𝟔𝟔𝟔𝟔𝟔𝟔)𝒆𝒆 𝟖𝟖.𝟔𝟔𝟔𝟔𝟔𝟔𝟔𝟔𝟏𝟏𝟏𝟏−𝟓𝟓 (𝟖𝟖𝟖𝟖𝟖𝟖) = 2.04x10-7 cm Wafer Manufacturing From Sand to Silicon Sand MGS Wafer manufacturing starts with sand! 1. Carbon is used to react with sand at high temperature to generate crude silicon, called metallurgic grade silicon, with purity up to 99%. SiO2 + 2C Heat Si + 2 CO ----- (3.4) Quartzite Coal MGS Carbon monoxide 2. MGS is ground into powder to react with hydrogen chloride to form liquid silicon hydrochloride such as SiHCl3 (TCS), with purity up to 99.9999999%. Heat (300 oC) Si + 3 HCI SiHCL3 + H2 ----- (3.5) MGS Hydrochloride TCS Hydrogen (TriChloroSilane) From Sand to Silicon 3. TCS is then used to react with hydrogen at high temperature to form high purity (99.999999999%) polycrystalline silicon, called electronic grade silicon (EGS). SiHCL3 + H2 Heat (1100 oC)Si + 3 HCI ----- (3.6) TCS Hydrogen EGS Hydrochloride Now the EGS is ready of crystal pulling to form single-crystal silicon ingot to be cut into wafer for IC processing. EGS Crystal Growth 2 common methods used to produce single-crystal silicon are: i. Czochralski (CZ) method ii. Float zone method The CZ method is more popular. Only CZ method can produce wafers larger than 200mm. It has relatively low cost. And it is capable of making heavily doped-single crystal silicon. The Float zone method is used for extremely high purity silicon. Figure 3.16 Schematic and photograph of Czochralski Both processes take place in a sealed growth systems furnace chamber in argon (Ar) ambient. Goto page 36 Crystal Growth – CZ method EGS is melted in a slowly rotating quartz crucible at 1415oC (melting point of Si = 1414oC) by radio frequency (RF) or resistive heating coils. A single-crystal silicon rod, called the seed (~ 0.5 cm in diameter, 10 cm long) is mounted on a slowly rotating chuck and gradually lowered into the molten silicon (rotating in the opposite direction). The surface of the seed starts to melt. The seed temperature is precisely controlled at just below the melting point. When the system reaches thermal stability, the seed crystal is withdrawn very slowly, dragging some molten silicon to recondense around it to form crystal with the same crystal orientation. Figure 3.17 Czochralski growth process Crystal Growth – CZ method http://www.youtube.com/watch?v=dvKKvQQsrSc Figure 3.18 Time lapse sequence of Si crystal being pulled from the melt in a CZ growth Crystal Growth – CZ method After ~ 48 hrs of pulling, a whole piece of single-crystal silicon called the ingot is formed. Modern wafer manufacturing plants can produce ingot with diameter over 300mm and a length of 1 to 2 m. Generally, the larger the required diameter, the slower the pull rate. The is because the heat loss is proportional to the surface area, which is proportional to the diameter of the crystal, while the energy produced by fusion is proportional to the volume, which in turn is proportional to the square of the diameter (eq 3.7). However, if the pull rate is too low, point defects will agglomerate to form dislocation loops. These loops, called swirls, are often distributed in swirls about the center of the wafer. Figure 3.19 ingot Crystal Growth – CZ method There is a maximum rate at which the crystal can be pulled. k dT Vmax = cm / s ----- (3.7) ρL dx where k is the thermal conductivity of silicon (0.21 W/cmK) ρ is the density of silicon (2.33 g/cm3) L is the latent heat of fusion (340 cal/g) dT dx is the temperature gradient in the solid silicon(K/cm) If the crystal is pulled faster than this, the solid silicon cannot conduct heat away faster enough for the molten silicon to solidify to form a single crystal. Example: Calculate the maximum rate for pulling up Si ingot at a temp gradient of 50K/cm. Latent heat of fusion, L= 340 cal/g=340 x 4.184 J/g= 1422.56 J/g 𝒌𝒌 𝒅𝒅𝒅𝒅 𝟎𝟎.𝟐𝟐𝟐𝟐 𝑽𝑽𝒎𝒎𝒎𝒎𝒎𝒎 = ρ𝑳𝑳 = 𝟐𝟐.𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑𝟑.𝟓𝟓𝟓𝟓 𝟓𝟓𝟓𝟓 = 𝟑𝟑. 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏−𝟑𝟑 cm/s 𝒅𝒅𝒅𝒅 Crystal Growth – CZ method The crystal quality is sensitive to pull rate. The material near the melt has very high density of point defects. Rapidly cooling the solid will prevent these defects from agglomerating. But this will create large thermal gradients, which stresses the crystal. For this reason, initial pulling rate is fast to provide rapid cooling required to minimize dislocations. The melt temperature is then lowered and the pull rate reduced to shoulder out the ingot to the desired diameter. This way, any dislocations/defects in the seed crystal, whether there initially or caused by contact with the molten silicon, can be prevented from propagating into the ingot. Figure 3.20 ingots of different crystallographic orientations Crystal Growth – CZ method (a) (b) (c) Figure 3.21 (a) Silicon growth facility, (b) Single crystal Si ingot (c) 300 mm wafers Crystal Growth – CZ method During the process of CZ growth, it is common to introduce dopant atoms into the melt so that a particular resistivity wafer can be made. To do this, one can simply weigh the EGS, determine the number of impurity atoms needed, calculate the weight of that number of impurity and add it to the melt. The rotation and melting of the seed improves the dopant uniformity in the ingot. However, impurities tend to segregate at the solid/liquid interfaces. That is, the solid silicon may be more, or less, likely to contain an impurity than the liquid silicon. Segregation coefficient k is defined as: Cs k= ----- (3.8) Cl where Cs and Cl are the impurity concentrations at the solid and liquid sides of the solid/liquid interface. Crystal Growth – CZ method If k 200 mm) is grounded on the ingot to (a) mark the crystal orientation (b) to serve as alignment guide for the wafer during subsequent photolithography Figure 3.27 Single-crystal ingot steps after end cutting, round grinding & flat/notch grinding Flat Grinding The largest flat, called the primary flat, is oriented perpendicular to the direction. One or more minor flats may be ground. Figure 3.28 Standard flat orientations for different wafers Wafer Preparation (2) Slicing The ingot is sliced into separate wafers. 2 common methods used: i. Inner diameter sawing The wafers are sliced by moving the Figure 3.29 Inner diameter sawing ingot radially outward in a rapid rotating inward-diameter diamond- coated saw. ii. Multiple wire slicing Wires coated with diamond dust is used to slice the wafers Figure 3.30 Multiple wire sawing Wafer Preparation (2) Slicing Wafer are sawed as thin as possible. However, they must be thick enough to sustain the mechanical handling in wafer processing. The larger the diameter, the thicker the wafer. Wafer Size (mm) Thickness (um) Weight (g) 150 (6”) 675 27.82 200 (8”) 725 52.98 300 (12”) 775 127.62 Table 3.2 Wafer thickness for different wafer size. (3) Surface grinding I. Improve the geometry of the wafer thickness tolerance and total thickness variation II. Reduce the subsurface crystal damage introduced during slicing Wafer Preparation (4) Edge Rounding The wafers are edged rounded so that they are less susceptible to defects created by mechanical handling during subsequent processing Figure 3.31 Edge rounding (5) Laser Marking Using laser, deep marks can be applied to either or both sides of the wafer surfaces. Shallow or soft marks can be applied to only the front side. Figure 3.32 Example of laser marking Wafer Preparation (6) Double-sided Lapping Wafers are mechanically lapped in a slurry of alumina and glycerine Figure 3.33 Double-sided lapping (7) Cleaning and Etching Cleaning removes particle, metals, and other contaminants Etching removes subsurface crystal damages Figure 3.34 Cleaning and etching Wafer Preparation (8) Thermal Donor Annealing involves a short heat treatment above 600°C and a quick run through the critical temperature of 450 ° C by appropriate cooling to avoid formation of new thermal donor - Rapid Thermal Annealing (RTA) Donor annealing is required so that the real resistivity of the monocrystal can be measured Oxygen can act as thermal donor Figure 3.35 Thermal Donor Annealing in monocrystal silicon. Only lowly doped wafer need to be annealed. Wafer Preparation (9) Chemical Mechanical Polishing (CMP) a chemical mechanical process involving a slurry of NaOH and very fine silica particles Polished surface is mirror like Goals of wafer polishing are I. Reduction of surface roughness II. Removal of surface and subsurface defects Figure 3.36 Wafer polishing III. Obtain desired geometry parameter - thickness, total thickness variation, flatness (10) Epitaxy growing of a monocrystalline layer on a monocrystalline substrate Homoepitaxy is when the layer and the substrate are made of the same material Heteroepitaxy is when the layer and the substrate are of different materials Substrate: polished Si wafer, Si source in epitaxy deposition: SiHCl3 (trichlorosilane) What we’ve covered … 1) Introduced some semiconductor basics 2) Crystal structure and 4 kinds of defects 3) Calculate defects (vacancy concentration) given temperature Nov = No e −Ea / kT denuded zone width given solubility of oxygen as a 1.2 gettering agent − 1.032 − Cox = 2 x 10 e 21 kT 3 / cm Ld = 0.091 t e kT 4) Ingot crystal growth through CZ and Floatzone method 5) Calculate Concentration of dopants at % completion of ingot growth Cs = kCo(1-X)k-1 Maximum velocity k dT Vmax = cm / s ρL dx 6) Wafer preparation from ingot to wafer k: Boltzman constant 8.617x10-5 eV/K k: impurity segregation coefficient k is the thermal conductivity of silicon (0.21 W/cmK)