CZ1105 Digital Logic PDF

CZ1105 - Digital Logic Summarised Notes Table of Contents: Table of Contents: 1 Chapter 1: Introduction 2 Chapter 2A: Number Systems 3 Chapter 2B: Codes 5 Chapter 3A: Boolean Bas...

CZ1105 - Digital Logic Summarised Notes Table of Contents: Table of Contents: 1 Chapter 1: Introduction 2 Chapter 2A: Number Systems 3 Chapter 2B: Codes 5 Chapter 3A: Boolean Basics 8 Chapter 3B: Logic Gates 9 Chapter 4: Digital Arithmetic 15 Chapter 5: Combinational 19 Chapter 6: Digital Circuits 21 Chapter 7A: Schmitt Trigger 25 Chapter 7B: Combinational Circuits 26 Chapter 8A: Introduction to Verilog (Structural) 28 Chapter 8B: Behavioral Verilog 32 Chapter 9: Sequential Circuits 35 Chapter 10: Sequential Circuit in Verilog 39 Chapter 11: Finite State Machines 42 Chapter 12: FSM in Verilog 44 1 Chapter 1: Introduction Digital vs Analog Analog ○ Quantities happen in nature around us ○ Quantity changes in a continuous manner over time Digital ○ Quantities are countable such as number of people, amount of school fees ○ Quantity changes in discrete steps Quantisation The conversion of analog values to digital format. However, precision is lost in the process. Advantages of Digital over Analog Techniques Easier to design Storage of information is easy Greater accuracy & precision Programmability Less susceptible to circuit noise Very Large Scale Integration (VLSI) technology Digital Data Transmission Data in bits can be transmitted from one device to another in: ○ Serial - e.g. 1 line, 1 bit at a time. Slower, but low cost ○ Parallel - e.g. 4 lines, 4 bits at a time. Faster, but higher cost 2 Chapter 2A: Number Systems Common Number Systems Name Symbols Decimal (base 10) 10 symbols 0,1,2,3,4,5,6,7,8,9 Binary (base 2) 2 symbols, 0, 1 Octal (base 8) 8 symbols, 0,1,2,3,4,5,6,7 Hexadecimal (base 16) 16 symbols 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F Position value system Each digit carries a weight. Left side is the MST (Most significant digit) Right side is the LSD (Least significant digit) Weight is carried by a base-N digit of the position (p=01,2…) given by N^p Conversions Base-N to Base-10: 1. Multiply each digit of the base-N number by its positional weight 2. Sum together the products obtained in 1 3 Base-10 to Base-N: 1. Divide base-10 number repeatedly by N until a quotient of 0 is obtained 2. Write down the remainder after each division 3. First remainder is the LSD, Last remainder is the MSD Conversion from hex (octal) to binary 1. Replace each hex (octal) digit by the corresponding 4-bit (3-bit) binary equivalent) Conversion from binary to hex (octal) 1. Starting from the LSB, replace every 4 bits (3bits) by the corresponding hex (octal) digit 2. Pad MSB with 0s if necessary 4 Chapter 2B: Codes Straight binary coding Numbers are the most common type of information that need to be represented Common to represent numerical value in binary ○ E.g. decimal value 35 is represented as 0010 0011 in binary. ○ This is called straight binary coding (aka binary coding) Binary-Coded Decimal-Code (BCD) Encode decimal numbers; combines some features of decimal & binary systems Each digit of a decimal number is represented by a 4-bit binary digit Digits are 0,1,2,3,4,5,6,7,8,9 4 bits are required for each digit as largest decimal digit is 9 Illegal BCD codes Example: Represent 957 in BCD 1010 (10) 1011 (11) 9 = 1001 1100 (12) 5 = 0101 1101 (13) 7 = 0001 1110 (14) 1111 (15) 957 = 1001 0101 0001 in BCD Compared to 11 1011 1101 in Straight binary Gray Code Belongs to a class of codes called minimum-change codes Only 1 bit in the code group changes when going from 1 to the next Unweighted code: Bit positions do not have any specific weight Usually cyclical: the last code word and the first codeword only has 1 bit difference 5 Useful in situations where multiple bit change may lead to error Not suitable for arithmetic operations Alphanumeric Codes Codes that represent ○ Alphabet ○ Punctuation marks ○ Special characters and numbers Complete set of alphanumeric code includes: ○ 26 lowercase letters (a-z) ○ 26 uppercase letters (A-Z) ○ 10 digits (0-9) ○ 7 punctuation marks ○ 20-40 other characters like + - / < # %... ASCII Code Most widely used alphanumeric code 7-bit code, 128 (2^7) possible code symbols Also the 8-bit extended ASCII code Used to transfer alphanumeric data between digital devices Used in digital computers to store alphanumeric characters (No need to memorize ASCII table) Example: Mp3 encoded into ASCII becomes: *Note: lower and UPPER case characters have different codes Often, hexadecimal digits used to reprsent ASCII codes. 6 Parity Bit Extra bit attached to a code group Forms part of code being transmitted Made of either 0 or 1 Able to detect single bit error only Receiver and transmitter must agree to odd/even parity scheme Limitation: Can only detect single bit error. But multiple bit errors are less likely to happen than single bit errors Even Parity bits Odd Parity bits Make total no. of "1" bits even before Make total no. of "1" bits odd before transmitting transmitting 7 Chapter 3A: Boolean Basics Boolean Constants Only 2 values ○ TRUE / FALSE ○ Logic HIGH / Logic LOW ○ HI / LO ○ 1/0 Boolean (logic) variables can only assume one of the two values Common logic level - voltage rangers ○ Voltage is partitioned 0-0.8V as logic 0, 2-5V for logic 1 (TTL) 0-1.5V for logic 0 and 3.5-5V for Logic 1 (CMOS (74AC)) ○ Should not use the voltage in-between as it is Indeterminate Typical logic circuit 1 or more logic input 1 or more logic output Output related to input by logic functions Truth Table Logic function fully described by truth table Truth table ○ Shows how a logic circuit output responds to various combination of logic input ○ Has 2n number of input combination for n inputs ○ Lists possible input combinations in accordance with binary counting sequence ○ There are 2(No. of inputs) rows in a logic gate. So for 2 inputs there are 22 i.e. 4 rows, for 3 inputs there are 23 i.e. 8 rows, and for a 4 input logic gate there are 24 i.e. 16 rows. 8 Chapter 3B: Logic Gates Basic Summary Type Description OR output is 1 when any of the inputs is 1 AND output is 1 when all the inputs are 1 NOT output is 0 when input is 1 and vice versa NOR output is 0 when any of the inputs is 1 NAND output is 0 when all the inputs are 1 XOR output is 1 if both inputs are different XNOR output is 1 if both inputs are the same Basic Logic Operations Logical Addition - OR Logical Multiplication - AND Logical complement/inversion - NOT These are realized by electronic devices called logic gates in digital circuits OR Gate X=A+B X = A OR B 2 Input OR gate X = A + B 3 Input OR gate X = A + B + C OR operation - as long as one input is 1, the output is 1 Only when both inputs are 0, the output is 0 X=A+B+C 9 AND Gate X=A*B X = A AND B X = AB 2-Input AND gate: X = AB 3-Input AND gate: X = ABC AND Operation result will only be 1 if all inputs are 1 NOT Gate NOT gate only has one input and is commonly known as an inverter Output is the complement/inverse of the input X=A' NOT gate basically flips the output. If input is 0, output is 1. If input is 1, output is 0. Buffer No change in logic The input = Output 10 NAND Gate (AB)’ = A’+B’ NAND Gate gives an output of 1 as long as both outputs are not 0. (Basically the opposite of an AND gate) NOR Gate X = (A+B)’ = (A’B’) NOR Gate outputs 1 if and only if both inputs are 0. XOR Gate Aka exclusive OR gate X = AB’+A’B’ X = A⊕B XOR Gate outputs 1 if and only if 1 of the inputs is 1. It outputs 0 even when both inputs are 1 11  XNOR Gate Aka exclusive NOR gate X = AB + A’B’ X = (A⊕B) XNOR Gate outputs 1 if and only if both inputs are the same Timing Diagrams Show the input and output using a line. In normal circumstances we draw using straight lines, but in reality, some propagation delays will be present (time to rise voltage from low to high and vice-versa) Boolean Algebra Order of precedence in boolean algebra 1. Inversion 2. Expression within parenthesis () 3. AND 4. OR Boolean Theorem Type Example Axioms X = 0 if X ≠ 1 X = 1 if X ≠ 0 0·0=0 1·1=1 0·1=1·0=0 1+1=1 0+0=0 1+0=0+1=1 Single variable theorems X 0=0 12  X 1=X X X=X X X’ = 0 X+1=1 X+0=X X+X=X X + X’ = 1 (X’)’ = X Commutative Laws A+B=B+A A B=B A Associative Laws A + (B + C) = (A + B ) + C = A + B + C A(BC) = (AB)C = ABC Distributive Laws A(B + C) = AB + AC (A + B)(C + D) = AC + BC + AD + BD Absorption Laws A + AB = A A + AB = A(1 + B) =A 1=A A + A’B = A + B A + A’B = A + AB + A’B = A + (A + A’)B = A + (1) B =A+B Consensus AB + A’C + BC = AB + A’C BC = ABC + A’BC Thus AB + A’C + BC = AB + A’C + ABC + A’BC = AB + ABC + A’C + A’BC = AB (1+C) + A’C(1+B) = AB + A’C De Morgan (A + B)’ = A’ B’ Invert the terms inside the parentheses and change the AND to OR (and vice versa) 13 Universality of NAND and NOR gates NAND gates can be used to form AND gate, OR gate and NOT gate. NAND & NOR gates can be used to implement any boolean function Equivalence proved by DeMorgan’s theorems NAND Gates NOR Gates output is 0 when all the inputs are 1 output is 0 when any of the inputs is 1 output is 1 when any of the inputs are 0 output is 1 when all of the inputs is 0 14 Chapter 4: Digital Arithmetic Adders Half adder Full adder Combinational logic circuit that performs Combinational logic circuit that performs addition of 2 bits addition of 3 bits Carry: AB Carry: AB + BCin + ACin Sum: A⊕B Sum: A ⊕ B ⊕ Cin n number of full adders are required for additional operation on two n number of bits. Parallel Adder N-full adders cascaded to form an N-bit parallel adder (aka ripple adder) All of the bits of the augend and addend are fed into the adder circuits simultaneously Addition fast, but limited by propagation delay of the Full Adders (carry propagation) Signed Numbers Sign bit is the MSB ○ 0 for +ve numbers ○ 1 for -ve numbers Equal numbers of positive and negative values N bit value lies in the range of: { -(2N-1 – 1) to +(2N-1 – 1) } 2’s complement 1s complement of the binary expression + 1 ○ 1s complement → replace all the 1s to 0s 15  ○ Add 1 to it (arithmetically) Easy conversion technique ○ Starting from LSB, copy bit if it is ‘0’, repeat with remaining bits ○ Copy the bit if it is the first ‘1’, invert remaining bits There is 1 more negative value than positive in 2s complement ○ N-bit value lies in the range of: { -(2N-1) to +(2N-1-1) } ○ i.e. 4 bits {-8 to 7}, 8 bits {-128 to 127} Representing signed numbers in 2’s complement system Number is 0 or positive Number is negative Represent magnitude in binary Represent magnitude in binary Append sign bit (0) in front of the MSB Obtain 2’s complement if the MSB is 1 Append sign bit (1) in front of the MSB if MSB is 0 Most positive: Most negative: 0111..11 1000...00 Obtaining decimal value of 2’s complement number Positive Negative Perform binary-to-decimal conversion Perform 2’s complement to convert to on the number positive Perform binary-to-decimal conversion on the positive number Observations of 2’s complement 2’s complement of an N-bit binary number is also of N bits Represent binary number with N significant bits in its magnitude using the 2’s complement, we need (N+1) bits for the sign bit If more bits than necessary to represent binary number in 2’s complement, remaining empty bits are filled with the sign bit (known as sign extension) 2’s complement will change positive number to negative and vice-versa with no change in the magnitude except: ○ Dealing with most negative number that can be represented given a number of bits 16 Reasons of 2’s complement Subtraction of numbers can be carried out in the same way as addition ○ (e.g. 9-7 is the same as 9+(-7)) Same set of hardware circuits can be used for subtraction and addition Arithmetic Overflow Occurs when arithmetic operation between two n-bit operands produces result that cannot be sufficiently represented by N bits. Operation Operands Addition Risk of overflow if operands have same sign Subtraction Risk of overflow if operands have different sign Detecting Overflow Occurs if the number of bits is not enough to represent the result accurately e.g. addition of two positive signed numbers results in a -ve representation due to the limit in the number of bits. Combined circuit for addition and subtraction Add sub indicates whether it is an addition/subtraction operation (1 is subtraction) XOR gates convert the 2nd number into the 1s complement by inverting the 0s and 1s (Logic of XOR gate returns 1 when the inputs are different, 0 when the same) Add sub is fed into the FA to represent the arithmetic addition of 1 to form the 2s complement Propagation delay is dependent on number of FA Binary Multiplication Multiply the top term by each bit of the bottom term, starting from the LSB Add them together TIP: Compute the sum of 2 of the results before moving on to the next to avoid confusion n bit * y bit, resultant is expected to be n+y bits 17 Binary Multiplication (Signed) Similar to the unsigned binary multiplication Need to perform sign extension If the multiplier is negative, the last partial product is the 2’s complement of the multiplicand BCD Addition Sum of two BCD digits does not exceed 910 operation is the same as binary addition. Otherwise, correction needs to be made by adding 6 (0110) to skip over the 6 invalid codes. 18 Chapter 5: Combinational Forms of Boolean Expressions Canonical Form ○ Sum of minterms (SOm) ○ Product of maxterms (POM) Standard Form ○ Sum of products (SOP) ○ Product of sums (POS) Minterms, Maxterms Uniquely describe the input combination at a given time instant Minterms Maxterms Yield logic 1 in truth table Yield logic 0 in truth table Boolean variables ANDed together Booolean variables ORed together Denoted by m15 (15 meaning input logic 1111) Denoted by m2 (2 meaning input logic 0010) Sum of products (SOP) Product of Sums (POS) Example: Example: Σ XYZ (1, 2, 4, 7) π XYZ (0, 3, 5, 6) X’Y’Z + X’YZ’ + XY’Z’ + XYZ (X+Y+Z) (X+Y’+Z’) (X’+Y+Z’) (X’+Y’+Z) Karnaugh Map Gray Code is used top to bottom Can only group in multiples of 2n (i.e. 2,4,8 but not 6) Group 1 for SOP Group 0 for POS Looping in K-Maps - POS B is always 0, and D is always 0. But A is 1 and 0 and C is 1 and 0, so A and C do not matter. Hence, B'D' A and B are always 0, whereas C and D change between 1 and 0, so C and D do not matter. Hence, A'B' B is always 1, and D is always 1, whereas A and C change between 1 and 0, so A and C do not matter. Hence, BD 19 Looping in K-Maps - SOP Loop 0s instead TAKE NOTE: 0 will be A and 1 will be A’ as we are looping 0s For 5 variable K-Maps Split up into two 4-variable K-Maps Each of the two 4-variable K-Maps will represent a 1 and 0 for the 5th variable respectively Group the 2 K-Maps as per normal Match up the groupings of the same coordinates, since A changes, it does not matter, and should not be included in the term Don’t Care conditions Conditions that do not matter as they will not happen Marked as X on the Kmaps Can be grouped as 1s or 0s for SOP and POS respectively 20 Chapter 6: Digital Circuits Transistors To make logic outputs switch between High and Low (1/0), transistors are used. Current flows from HIGH to LOW TTL - Transistor - transistor logic ○ Different in electrical characteristics such as power dissipation, delay time, switching speed CMOS - Complementary metal oxide semiconductor ○ Old series not compatible with TTL Bipolar junction transistors (BJT) MOS field-effect transistors (MOSFET) Base, emitter, Gate, drain, source collector With correct voltage at With correct voltage at G, current will flow B, current will flow between S and D between C and E Logic-Level Voltage Ranges TTL CMOS VCC nominally +5V VDD ranges from +8 to 18V +5V most often used when CMOS IC used in same circuit with TTL IC Unconnected (floating) inputs TTL CMOS Floating input acts like logic 1 Disastrous result Not recommended due to noise IC may become overheated pickup Unused input pins must be connected to VDD, GND or another input Active Levels Active High Active Low TRUE (asserted) when 1 TRUE (asserted) when 0 FALSE (negated) when 0 FALSE (negated) when 0 21 Parallel and Series Series - all transistors must be closed in order allow current to flow through Parallel - as long as one is closed, the current will flow through Bubble denotes the logic level for the transistor to close Voltage Parameters V for voltage I/O for input/output H/L for high/low Parameter Description VOH Minimum output voltage for logic 1 VIH Minimum input voltage for logic 1 VIL Max input voltage for logic 0 VOL Max output voltage for logic 0 Noise Margin Noise may affect the interpretation of the logic. The higher the noise margin, the better. High State → VOH - VIH Low State → VIL - VOL Current Parameters I for current I/O for input/output H/L for high/low Parameter Description IOH Maximum current that flows from output for logic 1 IIH Maximum current that flows to input for logic 1 IIL Minimum current that flows to input for logic 0 IOL Minimum current that flows from output for logic 0 Fan out 22  Specifies number of standard loads output gate can drive More loads reduce DC noise margin and switching speed Speed is time taken for output to switch from 0 to 1 Power dissipation P = C V2 f Propagation Delay Transition delay for signal to propagate from input to output tPHL Delay when output change from High to Low tPLH Delay when output change from Low to High tPLH/tPHL Measured from the 50% point of the input to the 50% point of the output. 50% is the half mark between high/low voltage Rise/Fall Time Time taken for signal to rise/fall from 0 to 1 or vice versa. Measured from 10% to 90% of final voltage Tristate outputs Logic 0 Logic 1 NEW Third state -- High impedance (Hi-Z) ○ Neither 0 or 1 ○ Behaves like an open circuit Open drain output Output is 0. An external pull-up resistor is required to make output 1 23 24 Chapter 7A: Schmitt Trigger Schmitt Trigger Inputs Characterised by 2 threshold Voltages VT-, VT+ Input voltage rises above VT+ Output switches to Low Input voltage falls below VT- Output switches to high Combinational PLA Programmable Logic Devices ○ Programmable Logic Array ○ Programmable Array Logic ○ Complex PLD ○ FPGA Field Programmable Gate array ○ SOM/SOP Boolean expressions can be easily implemented on a PLA 25 Chapter 7B: Combinational Circuits Combinational Circuits Are like functions, where the output is dependent on the current set of inputs Combinational Design Process Step 1: Capture the function Use a truth-table or equations, depending on what makes sense for the application Step 2: Convert to circuit Create the equations from the truth table in step 1 if applicable Create a circuit corresponding to that output’s equation Decoder Takes a binary input number, outputs corresponding one-hot output Only one output is high Position of the one-hot output corresponds to input value Output width is always 2n, where n is the number of inputs (i.e. 2 input decoder has 22 = 4 outputs) (Also referred to as n-m decoders) Internal design of a decoder Inverter branch for each of the inputs AND gate for each output to detect input combination Decoder with enable e e = 0 → outputs all 0 e = 1 → regular behavior Decoder Example: New Year’s Eve Countdown Display Processor counts from 59 to 0 in binary Convert 6-bit count to light up one bulb on the display ○ 59 needs 6 bits to represent in binary Hence, a 6-64 Decoder is used (4 outputs unused) ○ 6 inputs ○ 26 = 64 outputs 26 Multiplexers Selects one from multiple inputs. Consists of multiple inputs and a single output Select input(s) determine which input should be connected to the output 4 input mux requires a 2-bit select input n input mux requires log2(n)-bit select ○ Use base conversion formula since calculator dont support log2 log2(n) / log2(10) ○ NOTE: You may have to ceiling function the result. Check if the result means enough bits to support the input Select bit inputs must be the minimum number of bits required to represent the number of inputs The little dashes on the line represent the no. of bits for a connection Internal Design of a multiplexer Series of AND gates, connected to the inputs, and the corresponding desired select input Select inputs have an additional inverter to facilitate the AND gate logic 27 Chapter 8A: Introduction to Verilog (Structural) Hardware Description Language Describes hardware Enables hierarchical design Synthesized & optimized to hardware primitives Modules Designs broken into modules Container used to encapsulate functionality Declared using the module keyword & list of ports, direction indicated by input and output Modules end with endmodule keyword Gate-Level Primitives Verilog provides basic primitives to model boolean gates: and / nand / or / nor / not / xor / xnor Declaration (example used is and gate): and g1 (y, a, b, c); 1st argument is always the output, following arguments the inputs g1 is the name we assign to the gate Wire Declare internal wires in a module using the wire keyword Single bit wire aOut; Multi-bit (aka BUS) wire[3:0] //4 bit wire, wire MSB, wire LSB Notes Order does not matter in combinational verilog (it matters in sequential verilog) Verilog is case-sensitive Statements must be terminated with semicolon; Comments C-Style 28 Naming convention for identifier in Verilog Must start with letter or underscore Can contain alphanumeric characters and dollar sign ($) Must not clash with keywords (like wire/module) Module Instantiation in Verilog Instantiate module by invoking name and giving instance a name 2 ways to do this: Ordered Instantiation add_half M1 (a, b, w1, w2); //Instantiates an add_half module named M1, with arguments corresponding to order of module’s defined parameters (This is error prone) Named Instantiation add_half M1 (.a(a),.b(b),.sum(w1),. cout(w2)); //Instantiates an add_half module named M1. This time, we explicitly map the arguments to the parameters. -- format is.paramname(argument) Verilog Assignments Called continuous assignment as always permanently assigned Combinational logic expressions through assign keyword: assign y = a & b Verilog Assignment Operators Gate Logical Bitwise and && & or || | not ! ~ xor ^ ^ nand ~& nor ~| Bitwise vs Logical Bitwise → performs operation on the individual bits Logical → for use in logical statements 29 Verilog Operators Name Symbol Note Addition + Remember to add 1 more bit for addition Subtraction - 2’s complement subtraction Multiplication * Expected result addition of the the size of the multiplicands Exponent ** Division / Conditional Assignment Example: 2-input Multiplexer assign y = sel ? x1 : x0; Signal y will be connected to x1 if sel is 1 and x0 if sel is 0 Condition, result if condition is true, result if condition is false Vectors Basically multi-bit signals assign y = some ; //Assign 4th bit of some to y assign z = some[4:3]; //Assign the 5th and 4th bit to 2 bit signal z assign x = y; //assign 2nd bit of y to 1st bit of z assign x[2:1] = y[4:3]; //Assign range NOTE: Size of the vectors in assignments should match! Number Literals Used to assign fixed bit pattern to signal Anatomy: ’ → width in bits → type of number system → number you want, represented in selected number system Radix b → binary o → octal h → hexadecimal d → decimal 30 Examples 4’b0000 → 4 binary bits 0 0 0 0 8’h4F → equivalent to 8’b0100_1111 1’b1 → single 1 Notes: Assigning literal to larger signal, zero padded at MSB Assigning literal to smaller signal, MSBs are dropped where no space Concatenation Done using curly brackets and a list assign y = {a, b}; //a is the MSB, b is the LSB Replication Uses braces with preceding integer or variable representing an integer assign c = {{4{a}}, a[3:0]}; Replicates MSB 4 times, and concatenates a copy of a at the LSB assign c = {{4{1’b1}}, a[3:0]}; Replicates “1” 4 times, and concatenates a copy of a at the LSB Parameter Constant that is local to a module that can be declared in the module header or module body Can also be redefined in submodule instantiation 31 Chapter 8B: Behavioral Verilog Behavioral Verilog Describe how the circuit behaves, not how it is constructed Synthesis tools work out how to make hardware that fulfills description, taking into account target architecture Combinational always block Use a type of procedural block called an always block Contains procedural statements that describe behavior of desired hardware Sensitivity list must contain names of any signals that affect output of block If a signal is accidentally left out, expected circuit will not be attained Use shortcut: always @ * Covers all signals used Notes for combinational always block Never use assign keyword inside always block If more than one statement, use begin and end to define start/end of the block Signals assigned to from within always block must be declared of type reg Order matters for statements within the always block, so if sth is assigned more than once, the last assignment takes precedence Reg Signals assigned from within an always block must be declared of type reg Similar to wire, but can be assigned to from inside always block. Wires cannot Wire just a connection and holds not value Reg is more like variable Cannot assign to reg using an assign statement Can set initial value when declaring reg signals Can declare outputs as reg if assigned directly from within always block 32 What is synthesized? Assignments in always block exactly the same as assignments using an assign: If Statement Remember to include a begin-end keyword in each branch Case Statement Remember to add begin and end statements if branch has more than one statement Whole case block is usually treated as one statement, may not be necessary to enclose in a bein and end statement Signal Assignments from always block Can assign to multiple signal blocks If signal assigned from inside always block, should not assign it anywhere else (from assignment statements/other always blocks) Each always block represents logic that generate signal or set of signals 33  Group signals into single always block if it makes sense Order of always blocks do not matter Avoiding Latches Provide default assignment at top of always block Otherwise we are declaring it in a manner that we are storing data Must not do it as it synthesises storage 34 Chapter 9: Sequential Circuits Sequential vs Combinational Combinational circuits produce an output that is only dependent on the current set of inputs Sequential circuits produce an output that is dependent on BOTH the current state of inputs, and previous state produced by previous inputs TLDR; Sequential circuits have memory, combinational circuits have no memory. Sequential Logic Feedback loop can be added to an OR gate. However, this causes it to store 1 forever in an infinite loop Set-Reset Latch Basic circuit for storing a bit Made using two NOR gates Problem: When both Set and Reset are asserted at same time, oscillation occurs which eventually stops as 1 gate is faster than the other. But can damage circuit Solve by including an additional inverter and an AND gate? Problem: signals take time to travel through to gates, call to R is longer than call to S. 35 Gate/Enabled SR Latch Only respond to inputs when Enable is high. Ensure S and R never both high when E high. Transparent D Latch Remove the possibility of invalid input. Inverter ensures Reset is always opposite of Set Single input controls both states of the latch Passes its input through to its output when enable input is high Output is held when enable is low Active-Low Latches Swap NOR → NAND Swap OR → AND Propagation Delay Signal takes an amt of time to pass through each gate -- called propagation delay Delay may differ between different inputs, depending on number of gates they have to pass through Propagation delay can be given for each input-output pair If reporting single number, use worst-case scenario (i.e. longest delay) Clock Sequential components connected to a “Clock” Continuously toggles between 1 and 0 at fixed rate MHz and GHz represent number of cycles per second -- frequency 36  Period is the time it takes to complete cycle, frequency is 1 divided by period (giving us the frequency) Timing of latches A chain of normal latches will only allow the signal to propagate through if the clock signal is longer Hence, we introduce edge-triggered flip flips Edge Triggered Flip Flops At each rising edge, flip flop will take D input and produce value on Q output Represented by a box with triangle at bottom Implemented using 2 flip-flops in a Master-Slave configuration When clock is low, enable for master is on, propagating D value to the input of the slave flip flop (store inbetween) When clock rises to high, enable for master is switched off, and the enable for the slave is switched on The slave then propagates the signal through to Q In negative-edge triggered setup: master responds to high enable slave to low enable (move the inverter from enable of master to enable of slave) Represented by bubble infront of triangle Note Latch is level-sensitive Flip-flip is edge-triggered (can be posedge or negedge) Other Flipflops JK Flip Flop Output is 1 if J is asserted at rising edge and 0 if K is asserted If both asserted, output toggles (switches to the opposite) at rising edge 37 T Flip Flop Q toggles at rising edge if T = 1 Registers Combine multiple D flip-flops together to store multiple bits, also called a register Show values in a timing diagram without splitting up the bits, use decimal or hex, but make it clear Transitions only occur at rising edge 38 Chapter 10: Sequential Circuit in Verilog Registers in Verilog Remember reg keyword mentioned earlier, it is also the keyword for a register reg q → creates 1 bit register called q Always block format in sequential circuits New sensitivity list Instead of using always @ * we use always @(posedge clk) Indicate block’s behavior only occurs at clock rising edge, creating a flip flop/register For falling-edge triggered, use always @ (negedge clk) Reset We may want to reset the value in a register -- there are 2 types of reset Asynchronous Synchronous Resets the moment reset is asserted Resets on the rising edge of the clock (preferred) Assignments in Synchronous Always Blocks New assignment operator: