Fundamentals Of Computing Lecture 7 PDF

Sri Lanka Institute of Information Technology Faculty of Computing Fundamentals of Computing Dr.sanvitha kasturiarachchi Year 01 and Semester 01 Year 01 and Semester 01 1 / 39  Lecture 7 Proc...

Sri Lanka Institute of Information Technology Faculty of Computing Fundamentals of Computing Dr.sanvitha kasturiarachchi Year 01 and Semester 01 Year 01 and Semester 01 1 / 39  Lecture 7 Processor Components Year 01 and Semester 01 2 / 39 Lecture Learning Objectives Understand and explain the components of a processor. Understand the different addressing modes. Understand the instructions and the interrupts. Understand and explain the input output operations. Year 01 and Semester 01 3 / 39 Outline 1 Simple processor Control Unit ALU Registers 2 Addressing modes 3 Instructions 4 Interrupts 5 Input/output operations Year 01 and Semester 01 4 / 39 Simple processor A processor contains three units: Control Unit Arithmetic Logic Unit Registers Year 01 and Semester 01 5 / 39 Control Unit What control unit is? Operations of Control Unit Year 01 and Semester 01 6 / 39 Control unit Control unit manages the overall operation of the computer. It includes fetching the next instruction from memory, decoding the instruction to determine the operation to perform, and distributing the execution of the instruction to Arithmetic and Logic Unit of the processor. Year 01 and Semester 01 7 / 39 Operations of Control Unit Control unit reads the data word at the memory address indicated by the Program Counter (PC) and places it in an internal register for decoding and execution. It reads additional memory locations following the opcode based on the opcode bit pattern. Then the control unit may retrieve data needed by the instruction, such as a memory address or data operand. Year 01 and Semester 01 8 / 39 Arithmetic and Logic Unit (ALU) What ALU is? Key components of ALU Operations of ALU Year 01 and Semester 01 9 / 39 Arithmetic Logic Unit The Arithmetic Logic Unit (ALU) is often considered the ”brain within the brain” of the CPU, as it handles the core computational tasks that drive the functionality of a computer. The ALU operates under the direction of the control unit. The results of ALU operations are typically stored in registers or memory, depending on the instruction being executed. Year 01 and Semester 01 10 / 39 Key components of ALU Operands: The input data values that the ALU processes. Operands are typically fetched from CPU registers or memory. Operators: The ALU uses a set of predefined operations (operators) to perform computations on the operands. These include arithmetic operators (e.g., addition, subtraction) and logical operators (e.g., AND, OR). Control Signals: The ALU receives control signals from the control unit, which dictate the specific operation to be performed. These signals are based on the instruction currently being executed by the CPU. Flags and Status Registers: The ALU may produce status flags as a result of its operations. These flags indicate conditions such as zero result, overflow, carry, or negative result, which can affect subsequent operations or control flow. Year 01 and Semester 01 11 / 39 Operations of ALU Arithmetic and Logic Unit performs a variety of operations related to arithmetic and logic functions. Arithmetic operations Logical operations Shift operations Comparison operations Bitwise operations and etc. Year 01 and Semester 01 12 / 39 Processor Registers What Registers are? Functions of Processor Registers Types of Processor Registers Operations of Processor Registers Year 01 and Semester 01 13 / 39 Processor Registers Processor registers are small, fast storage locations within a CPU that hold data, instructions, addresses, and other information necessary for the execution of programs. They are an essential part of the CPU’s architecture and are used to quickly access data that is being actively processed or managed by the CPU. Year 01 and Semester 01 14 / 39 Functions of Processor Registers The primary functions of registers include: Holding operands for arithmetic and logic operations. Storing the results of computations. Keeping track of memory addresses. Managing control information for program execution. Year 01 and Semester 01 15 / 39 Types of Processor Registers Data Registers General purpose registers Special purpose registers Address Registers Memory address registers Index registers Stack pointer Control Registers Status Register/Flags Register Program counter Instruction register Year 01 and Semester 01 16 / 39 Types of Processor Registers (Cont..) Floating-Point Registers These are specialized registers designed to handle floating-point operations, which involve decimal and exponential values. They are essential for performing complex mathematical calculations in scientific computing. Segment Registers Segment registers hold the base addresses of segments in memory. This allows the CPU to access larger amounts of memory by combining segment registers with general-purpose registers. Year 01 and Semester 01 17 / 39 Types of Processor Registers (Cont..) The size of the registers determines the amount of data the processor can process at a time and influences the overall performance and capabilities of the processor. 8-bit Registers: Found in early microprocessors like the Intel 8080. 16-bit Registers: Used in Intel 8086 processor. 32-bit Registers: Common in more modern processors, allowing for wider data paths and larger addressable memory spaces. 64-bit Registers: Found in current-generation CPUs, supporting large data types and enhanced performance in computing tasks. Year 01 and Semester 01 18 / 39 Operations of Processor Registers Fetch: The CPU fetches the instruction from memory, using the Program Counter (PC) to determine the address of the next instruction. The instruction is then loaded into the Instruction Register (IR). Decode: The instruction in the IR is decoded, and the necessary operands are loaded into the appropriate registers from memory or other registers. Execute: The ALU or another processing unit performs the operation specified by the instruction, using data from the registers. The result is stored back into a register. Write-back: The result stored in a register is written back to memory or used in subsequent instructions. Year 01 and Semester 01 19 / 39 Processor Registers (Cont..) In modern CPU architectures, the number and type of registers can vary significantly. x86 Architecture: Typically includes 8 general-purpose registers and additional segment, control, and floating-point registers. ARM Architecture: Typically includes 16 general-purpose registers. RISC-V Architecture: Includes 32 general-purpose registers. These registers are used differently depending on the architecture, the operating system, and the specific application running on the CPU. Year 01 and Semester 01 20 / 39 Addressing modes Addressing modes are techniques used by the instruction set to specify the location of operands, the data on which the processor operates. These modes determine how the processor identifies the address of the data required for an operation. Year 01 and Semester 01 21 / 39 Types of addressing modes 1 Immediate Addressing Mode: The operand is directly specified in the instruction itself. The value is immediately available. Example: MOV R1, #5 (5 is an immediate value loaded directly into register R1) 2 Register Addressing Mode: The operand is located in a processor register. The instruction specifies the register that contains the operand. Example: ADD R1, R2 (Here, the contents of R2 are added to R1) Year 01 and Semester 01 22 / 39 Types of addressing modes Direct Addressing Mode (Absolute Addressing): The instruction contains the memory address of the operand. The CPU fetches the operand from the specified memory location. Example: MOV R1, (Here, the data at memory address 1000 is moved to register R1) Indirect Addressing Mode: The instruction specifies a register or memory location that contains the address of the operand. The CPU first fetches the address from this location and then accesses the operand at the resulting address. Example: MOV R1, [R2] (Here, the address stored in R2 points to the memory location where the operand is stored.) Year 01 and Semester 01 23 / 39 Types of addressing modes Indexed Addressing Mode: The effective address of the operand is obtained by adding a constant value (index) to a base address held in a register. Example: MOV R1, [R2 + 4] (Here, the address is calculated by adding 4 to the contents of R2, and the data at this address is moved to R1.) Year 01 and Semester 01 24 / 39 Processor Instructions Memory load and store instructions Register-to-register data transfer instructions Stack instructions Arithmetic instructions Logical instructions Branching instructions Subroutine call and return instructions Processor flag instructions Interrupt-related instructions No operation instruction Year 01 and Semester 01 25 / 39 Processor Instructions Cont. Memory load and store instructions This allows the CPU to retrieve data from memory (load) and save data back to memory (store). load instructions: LOAD R1, [address] store instructions: STORE [address], R1 Register-to-register data transfer instructions These are used to move data from one register to another within the CPU. MOV R1, R2 (Moves the contents of R2 to R1. Year 01 and Semester 01 26 / 39 Processor Instructions Cont. Stack instructions The stack instructions allow the CPU to push data onto the stack, pop data from the stack, and perform other stack-related operations. Arithmetic instructions These enable the processor to perform basic mathematical operations such as addition, subtraction, multiplication, and division. (ADD, SUB, MUL etc.) Year 01 and Semester 01 27 / 39 Processor Instructions Cont. Logical instructions These allow the processor to perform bitwise operations on data. (AND, OR, XOR (exclusive OR), and NOT) Branching instructions These instructions allow the CPU to ”branch” or ”jump” to a different part of the program, rather than executing instructions sequentially. Branching is essential for implementing control structures like loops, conditionals, and function calls. (JMP, LOOP) Year 01 and Semester 01 28 / 39 Processor Instructions Cont. Subroutine call and return instructions These instructions allow a program to temporarily divert execution to a subroutine/ function and then return to the original point of execution after the subroutine/ function has completed. Processor flag instructions This register holds various bits that indicate the state of the processor after executing an instruction, such as whether a result is zero, whether an arithmetic overflow occurred, or whether a carry out of the most significant bit occurred. Year 01 and Semester 01 29 / 39 Processor Instructions Cont. Interrupt-related instructions These are specific commands that handles interrupts. An interrupt is a signal to the processor indicating that an event needs immediate attention. Interrupts can be triggered by hardware or by software. No Operation instructions - NOP This is a CPU instruction that effectively does nothing. When a processor executes a NOP instruction, it moves the program counter to the next instruction without performing any computational or memory-related operations. Year 01 and Semester 01 30 / 39 Interrupts Interrupts are signals sent to the CPU. They tell the CPU to stop its current activities and execute the appropriate part of the operating system. There are three types of interrupts: Hardware Interrupts are generated by hardware devices to signal that they need some attention from the OS. Software Interrupts are generated by programs when they want to request a service from the Operating system. Traps are generated by the CPU itself to indicate that some error or condition occurred for which assistance from the operating system is needed. Year 01 and Semester 01 31 / 39 Input/output operations Input/Output (I/O) operations in a processor involve the transfer of data between the CPU and external devices, such as keyboards, displays, storage devices, or network interfaces. These operations are crucial for the interaction between the computer and the outside world, enabling the system to receive data (input) from peripherals and send data (output) to them. Year 01 and Semester 01 32 / 39 Input/output operations (Cont..) I/O Ports Each I/O device is assigned a unique port number, and the processor uses these ports to send or receive data. Memory-Mapped I/O In some systems, I/O devices are mapped directly into the regular memory address space. The processor can read from or write to an I/O device using standard memory access instructions. Year 01 and Semester 01 33 / 39 Input/output operations (Cont..) Programmed I/O (PIO) The processor is responsible for transferring data to and from I/O devices. This involves the processor actively checking the status of the I/O device and moving data between the processor registers and the device. Interrupt-Driven I/O The processor starts a data transfer operation and then continues with other tasks. The I/O device interrupts the CPU when it is ready to exchange data, allowing the CPU to handle I/O operations asynchronously. Year 01 and Semester 01 34 / 39 Input/output operations (Cont..) Direct Memory Access (DMA): DMA allows I/O devices to transfer data directly to or from memory without involving the processor in the data transfer. The processor sets up the DMA controller with the necessary information (source, destination, length), and the DMA controller handles the data transfer autonomously. DMA is highly efficient and is often used for high-speed data transfers, such as those involving disk drives or network cards. Year 01 and Semester 01 35 / 39 Summary Simple processor Addressing modes Instructions Interrupts Input/output operations Year 01 and Semester 01 36 / 39 End of lecture 7 Year 01 and Semester 01 37 / 39 Weekly Plan Practical: Simulation of electronic circuits - I Workshop: Proposal Evaluation Year 01 and Semester 01 38 / 39 Thank You! Year 01 and Semester 01 39 / 39