csc25-chapter_03b.pdf

CSC-25 High Performance Architectures Lecture Notes – Chapter III-B Pipeline Control Denis Loubach [email protected] Department of Computer Systems Computer Science Division – IEC Aeronautics Institute of Technol...

CSC-25 High Performance Architectures Lecture Notes – Chapter III-B Pipeline Control Denis Loubach [email protected] Department of Computer Systems Computer Science Division – IEC Aeronautics Institute of Technology – ITA 1st semester, 2024 Detailed Contents Simple Multiple Cycle Implementation Recap Basic Pipeline MIPS instruction layout Control the Pipeline Single Cycle Datapath Coping with Branches MIPS References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 2/44 Outline Recap MIPS References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 3/44 Recap MIPS instruction layout In the I-type instruction there is the Immediate, a 16-bit field In the J-type instruction there is the shift, 26-bit field, applied to PC (target address) MIPS instruction layout 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 4/44 Recap (cont.) Single Cycle Datapath Branch Instruction[31:0] Rd Rt RegDst Jump 1 0 Instruction [25:21] [20:16] [15:11] [15:0] Mux Fetch Unit Clk Rs Rt RegWr 5 5 5 AluCtrl Rs Rt Rd Imm16 BusW We Rw Ra Rb MemToReg busA 32× 32-bit A Zero Registers L Clk U 0 busB 0 MemWr Mux Mux 1 1 16 DataIn We Addr Sign Data Imm16 Extender Data AluSrc Memory ExtOp Clk 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 5/44 Recap (cont.) Single Cycle Datapath Addr[31:2] PC[31:28] “00” Addr[1:0] 4 Instruction + 1 Clk Memory Target 26 PC Instruction[25:0] Mux Clk 0 0 + Mux Instruction[31:0] “1” 1 + Jump Imm16 Sign Instruction[15:0] Extender Branch Zero 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 6/44 Outline Recap MIPS References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 7/44 MIPS Simple Multiple Cycle Implementation Every MIPS instruction can be implemented in at most 5 clock cycles: 1. instruction fetch - IF 2. instruction decode/register fetch - ID 3. execution/effective address - EX 4. memory access/branch completion - MEM 5. write-back - WB 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 8/44 MIPS (cont.) Simple Multiple Cycle Implementation Instruction flow through the datapath, multiple cycle implementation. PC is written during the memory access clock cycle and the registers are written during the write-back clock cycle 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 9/44 MIPS (cont.) Simple Multiple Cycle Implementation IF cycle 1 IR