Ch.4 instruction.pdf

The computer’s CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit. Control Unit CPU components perform sequenced operations according to control unit signals Datapath consists of = an arithmetic-logic unit + storage units...

The computer’s CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit. Control Unit CPU components perform sequenced operations according to control unit signals Datapath consists of = an arithmetic-logic unit + storage units (registers) interconnected by a data bus also connected to main memory. Registers o hold data that can be readily accessed by the CPU. o They can be implemented using D flip-flops. o A 32-bit register requires 32 D flip-flops. The arithmetic-logic unit (ALU): carry out logical and arithmetic operations as directed by the control unit. The control unit determines which actions to carry out according to o the values in a program counter register and o a status registers. The bus Benefit: CPU shares data with other system components Definition: bus is a set of wires that simultaneously convey a single bit along each line. Types: point-to-point, and multipoint buses. point-to-point buses A multipoint bus consist of Data Lines: convey bits from one device to another Control Lines: determine o the direction of data flow, and o when each device can access the bus. Address Lines: determine o the location of the source or o destination of the data. Because a multipoint bus is a shared resource, access to it is controlled through protocols, which are built into the hardware. Master-Slave Configuration more than one device can be the bus master, concurrent bus master requests must be arbitrated. Four categories of bus arbitration are: Daisy chain: Permissions are passed from the highest-priority device to the lowest. Centralized parallel: Each device is directly connected to an arbitration circuit. Distributed using self-detection: Devices decide which gets the bus among themselves. Distributed using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again. Clock Every computer contains at least one clock that synchronizes the activities of its components. A fixed number of clock cycles are required to carry out each data movement or computational operation. The clock frequency, measured in MHz or GHz, determines the speed of operations are carried out. Clock cycle time is the reciprocal of clock frequency. o An 800 MHz clock has a cycle time of 1.25 ns. Clock speed should not be confused with CPU performance. The CPU time required to run a program is given by the general performance equation: improve CPU: reduce the number of o instructions in a program, o cycles per instruction, o nanoseconds per clock cycle. The Input/Output Subsystem A computer communicates with the outside world through its input/output (I/O) subsystem. I/O devices o connect to the CPU through various interfaces. o can be memory-mapped o behaves like main memory from the CPU’s point of view. o can be instruction-based, where the CPU has a specialized I/O instruction set. Memory Organization Computer memory consists of a linear array of addressable storage cells that are similar to registers. Memory o can be byte-addressable, or word- addressable (> two bytes) o consists of more than one RAM chip o constructed of RAM chips = length * width. o memory word size = 16 bits = 4M * 16 RAM chip = 4 mega 16-bit memory locations. How does the computer access a memory location corresponds to a particular address? 4M = 22 * 220 = 222 words. The memory locations = 0 through 222 – 1. The memory bus = requires at least 22 address line o Count from 0 to 222 – 1 in binary o Each line is either “on” or “off” indicating the location of the desired memory element. Access efficient when memory = into banks of chips with the addresses interleaved across the chips o low-order interleaving = low order bits of the address in memory bank o high-order interleaving = high order address bits specify the memory bank. Example: Suppose we have a memory consisting of 16 2K x 8-bit chips. – Total Memory Size = Number of Chips × Chip Capacity = 16 × 2,048 bytes = 32,768 bytes (32K) – Chip Selection (Number of Chips): Number of Bits = log₂ (16) = 4 – Offset within Chip (Bytes per Chip): Number of Bits = log₂(2K) = 11 – 15 bits are needed for each address. EXAMPLE Suppose we have a 128-word memory that is 8-way low-order interleaved low-order = 8 = 23 → 3 bits to identify the bank. 128 = 27 MARIE Definition Purpose of illustrating basic computer system concepts. too simple to do anything useful in the real world uses a modified form of programmed I/O. Characteristics The MARIE architecture has the following: Binary, two's complement data representation. Stored program, fixed word length data and instructions. 4K words of word-addressable main memory. 16-bit o data words = 16-bit instructions, 4 for the opcode and 12 for the address. o arithmetic logic unit (ALU). Seven registers for control and data movement. Seven Registers Name 1 Accumulator, AC, 2 Memory buffer register, MBR, 3 Memory address register, MAR 4 5 6 Program counter, PC, Instruction registers, IR, Input register, InREG, Bit Hold register 16 conditional operator (e.g., "less than") or one operand of a two-operand instruction. 16 data after its retrieval from, or before its placement in memory. 12 memory address of an instruction or the operand of an instruction. 12 address of the next program instruction to be executed. instruction immediately preceding its execution 8 data read from an input device. 7 Output register, OutREG, 8 CPU polls the input register (InREG) until input is sensed, at which time the value is copied into the accumulator. data that is ready for the output device. All output is placed in an output register MARIE architecture The registers are interconnected, and connected with main memory through a common data bus. bus is identified by a unique number = control lines when device is required to carry out an operation. Separate connections are also provided between o the accumulator and the memory buffer register and o the ALU and the accumulator and o memory buffer register. This permits data transfer between these devices without use of the main data bus. Computer Instruction Set Architecture (ISA) format of instructions and the primitive operations that the machine can perform. interface between a computer’s hardware and its software. different instructions for processing data and controlling program execution. The MARIE ISA consists of only 13 instructions. MARIE direct addressing mode: address of the operand is explicitly stated in the instruction Microoperations instructions actually consists of a sequence of smaller instructions The exact sequence can be specified using register transfer language (RTL). In the MARIE RTL, we use the notation M[X] to indicate the actual data value stored in memory location X, and the transfer of bytes to a register or memory location (arrow). Skipcond Instruction When the Skipcond instruction is executed, the value stored in the AC must be inspected. Example: Two of the address bits specify the condition to be tested. o If the two address bits are 00 = “skip if the AC is negative.” o If the two address bits are 01 = “skip if the AC is equal to 0.” o if the two address bits are 10 = “skip if the AC is greater than 0.” instruction will be skipped if the value in the AC is greater than zero By “skip” we simply mean jump over the next instruction. Load instruction allows us to move data from memory into the CPU (via the MBR and the AC). First: data move into the MBR Second: then into either the AC or the ALU The Store instruction allows us to move data from the CPU back to memory. The add and subtract, Input and Output allow MARIE to communicate with the outside world. Load Instruction address X must first be placed into the MAR. Then the data at location M[MAR] is moved into the MBR. Finally, this data is placed in the AC. Add Instruction address X must first be placed into the MAR. Then the data at location M[MAR] is moved into the MBR. The data value stored at address X is added to the AC. Finally, this data is placed in the AC. Skipcond Depending on this bit combination, the AC is checked to see whether it is -, = 0, or +. If the given condition is true, then the next instruction is skipped. This is performed by incrementing the PC register by 1. If the bits in positions 10 and 11 are both ones, an error condition results. Instruction Processing (fetch-decode-execute) Memory → instruction (fetch) → IR (decoded) to determine what needs to be done next. If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. All computers provide a way of interrupting the fetch-decode-execute cycle. Interrupt processing involves adding another step to the fetch-decode-execute cycle Interrupts The normal execution of a program is altered when an event of higher-priority occurs. The CPU is alerted to such an event through an interrupt. Each interrupt is associated with a procedure that directs the actions of the CPU when an interrupt occurs. Interrupts can be triggered by o I/O requests, o arithmetic errors (such as division by zero), or o when an invalid instruction is encountered. o A user break (e.g., Control+C) is issued o I/O is requested by the user or a program o A critical error occurs Nonmaskable interrupts are o high-priority interrupts that cannot be ignored. o must be processed in order to keep the system in a stable condition. Maskable Interrupts that are ignored Interrupts are asynchronous and indicate some type of service is required. A computer’s control unit keeps things synchronized = bits flow to the correct components as needed. Interrupts can be caused by hardware or software = traps. For general-purpose systems = disable all interrupts during = interrupt is being processed. o By setting a bit in the flags register. Interrupts are very useful in processing I/O. However, interrupt-driven I/O is complicated, Discussion on Assemblers Mnemonic instructions = LOAD 104, o easy for humans to write and understand. o They are impossible for computers to understand. Assemblers translate instructions = comprehensible to humans into the machine language = comprehensible to computers assembly language, there is a one-to-one correspondence between a mnemonic instruction and code. create an object program file from mnemonic source code in two passes. o First pass, the assembler assembles program + builds a symbol table that contains memory references o Second pass, the instructions are completed using the values from the symbol table. indirect addressing, where the address of the address of the operand is given in the instruction. LOADI X and STOREI X = the address of the operand to be loaded or stored. The ADDI X where specifies the address of the operand to be added. Another helpful programming tool is the use of subroutines. JNS, gives us limited subroutine functionality. Control unit can be implemented: Microprogrammed Control, a small program is placed into read-only memory in the microcontroller. define the operation of MARIE’s control unit adaptable to changes. consists of a o distinctive signal pattern that is interpreted by the control unit o results in the execution of an instruction Hardwired Controllers implement this program using digital logic components. better performance the bit pattern of machine instruction in the IR is decoded by combinational logic. The decoder output works with the control signals of the current system state o to produce a new set of control signals. signal pattern hardwired controller = signal pattern microprogrammed control. Your text provides a complete list of the register transfer language for each of MARIE’s instructions. Each of MARIE’s registers + main memory = unique address (signals issued by the control unit.) + datapath. How many signal lines does MARIE’s control unit need? 15 single lines JNS jump-and-store instruction permit recursive calls? JUMP instructions are more direct but lack the structured control flow of CALL instructions. Let us define two sets of three signals. The register MBR is enabled for o reading when P0 and P1 are high, and o enabled for writing when P3 and P4 are high. ALU has only three operations: add, subtract, and clear, do nothing. The entire set of MARIE’s control signals consists of: Register Controls: o P0, P1, P2: signals control reading from memory or a register. o P5, P4, P3, signals control writing to memory or a register o MR: This signal enables the Memory Buffer Register (MBR) for reading. o MW: This signal enables the MBR for writing. ALU Controls: o A0, A1: These signals control the operations of the Arithmetic Logic Unit (ALU). o LALT: This signal controls the ALU’s data source. Timing and Counter Reset: o T0 through T7: These signals are related to timing and synchronization. o Cr: This signal is used for counter reset. These signals are ANDed with combinational logic → Instruction Fetch: o An Add instruction is fetched. o The address X is stored in the rightmost 12 bits of the Instruction Register (IR). o The IR has a datapath address of 7. Copying X to MAR: o The value of X needs to be copied to the Memory Address Register (MAR). o The MAR has a datapath address of 1. Control Signals: o P0, P1, and P2 for reading from the IR. o P3 for writing to the MAR. In the MARIE architecture, the IR has a total of 16 bits. o The 12 bits in the IR represent memory addresses or instruction operands. o The 7 refers to the IR’s datapath address. o The 1 refers to the MAR’s datapath address, where we want to copy the value of X. Instruction sets are differentiated Number of bits per instruction. Stack-based or register-based. Number of explicit operands per instruction. Operand location. number of operands per instruction Types of operations. Type and size of operands. Instruction set architectures are measured Main memory space occupied by a program. Instruction complexity. Instruction length (in bits). Total number of instructions in the instruction set. Design consideration Instruction length o short, long, or variable. o affected by the number of operands supported by the ISA Number of operands. Number of addressable registers. Memory organization = byte- or word addressable. Addressing modes = direct, indirect or indexed. Byte ordering, or endianness: little endian the least significant byte is followed by the most significant byte Makes it easier to place values on non-word boundaries. Conversion from a 16-bit integer address to a 32-bit integer address = not require arithmetic. Big endian the most significant byte first (at the lower address). Is more natural. The sign of the number can be determined by looking at the byte at address offset 0. Strings and integers are stored in the same order. CPU storage: stack + accumulator + general purpose register Selection criteria: cost of hardware design + execution speed + ease of use. accumulator architecture one operand of a binary operation is implicitly in the accumulator. One operand is in memory, creating lots of bus traffic. general purpose register (GPR) architecture registers can be used instead of memory. o Faster than accumulator architecture. o Efficient implementation for compilers. o Results in longer instructions. Most systems today are GPR systems. There are three types: o Memory-memory where two or three operands may be in memory. o Register-memory where at least one operand must be in a register. o Load-store where no operands may be in memory. The number of operands and the number of available registers has a direct affect on instruction length. Stack Architecture instructions and operands are implicitly taken from the stack. A stack cannot be accessed randomly. use one and zero operand instructions. LOAD and STORE instructions require a single memory address operand. Other instructions use operands from the stack implicitly. PUSH and POP operations involve only the stack’s top element. Binary instructions (e.g., ADD, MULT) use the top two items on the stack. postfix notation = reverse Polish notation Three-address ISA, (e.g., mainframes) the infix expression, One-address ISAs usually require one operand to be a register. Infix (X+Y) * (W+U) (2+3) – 6/3 Postfix XY+WU+* 23+63/- Operations that require no operands = HALT, waste some space when fixed-length instructions used. One way to recover some of this space is to use expanding opcodes. A system has 16 registers and 4K of memory. 4 bits to access one of the registers + 12 bits for a memory address. If the system is to have 16-bit instructions, we have two choices for our instructions: Example: Given 8-bit instructions, is it possible to allow the following to be encoded? – 3 instructions with two 3-bit operands = 3 * 23 * 23 = – 2 instructions with one 4-bit operand = 2 * 1 * 24 = – 4 instructions with one 3-bit operand = 4 * 1 * 23 = Total: 256 bits to encode our instruction set in 8 bits! Instructions fall into several broad categories that you should be familiar with: Data movement + Arithmetic. Boolean + Bit manipulation. I/O + Control transfer + Special purpose. Addressing modes specify o where an operand is located. o a constant, a register, or a memory location. The actual location of an operand is its effective address. Certain addressing modes allow us to determine the address of an operand dynamically. The addressing mode Immediate addressing is where the data is part of the instruction. Direct addressing is where the address of the data is given in the instruction. Register addressing is where the data is located in a register. Indirect addressing gives the address of the address of the data in the instruction. Register indirect addressing uses a register to store the address of the address of the data. Indexed addressing o uses a register (implicitly or explicitly) as an offset, o which is added to the address in the operand o to determine the effective address of the data. o holds an offset relative to the address given in the instruction Based addressing o base register is used instead of an index register. o holds a base address where the address field represents a displacement from this base. In stack addressing the operand is assumed to be on top of the stack. There are many variations to these addressing modes including: – Indirect indexed. – Base/offset. – Self-relative. – Auto increment—decrement. Instruction Pipelining CPUs divide the fetch-decode- execute cycle into smaller steps. executed in parallel to increase throughput = instruction pipelining. Instruction pipelining provides for instruction level parallelism (ILP) For every clock cycle, one small step is carried out, and the stages are overlapped Suppose a fetch-decode-execute cycle were broken into the following smaller steps: 1. Fetch instruction 2. Decode opcode 3. Calculate effective address of operands 4. Fetch operands 5. Execute instruction 6. Store result Conclusion The major components of a computer system are its control unit, registers, memory, ALU, and data path. A built-in clock keeps everything synchronized. Control units can be microprogrammed or hardwired. Computers run programs through iterative fetch-decode-execute cycles. Computers can run programs that are in machine language. An assembler converts mnemonic code to machine language. The Intel architecture is an example of a CISC architecture; MIPS is an example of a RISC architecture. Instructions can be fixed length or variable length. To enrich the instruction set for a fixed length instruction set, expanding opcodes can be used. CISC = Complex Instruction Set Computer MIPS = Microprocessor without Interlocked Pipeline Stages RISC = Reduced Instruction Set Computer MAR = Memory Address Register MBR = Memory buffer register IR = Instruction Register ALU = Arithmetic Logic Unit ISA = Instruction Set Architecture RTL = register transfer language AC = Accumulator PC = Program counter InREG = Input register OutREG = Output register ILP = instruction level parallelism simple architecture = MARIE = fetch–decode–execute cycle and how computers actually operate. The fetch–decode–execute cycle consists of the steps a computer follows to run a program. ISA + assembly language = write programs for MARIE. MARIE has 4K 16-bit words of main memory, uses 16-bit instructions, and has seven registers. Instructions for MARIE use 4 bits for the opcode and 12 bits for an address. The CPU consist of datapath (registers and an ALU connected by a bus) and a control unit that are responsible for sequencing the operations and data movement and creating the timing signals. All components use these timing signals to work in unison. The I/O subsystem accommodates getting data into the computer and back out to the user. There is only one general-purpose register, the AC. Register transfer notation = examining what each instruction does at the register level. An instruction is fetched and then decoded, any required operands are then fetched, and finally the instruction is executed. Interrupts are processed at the beginning of this cycle, returning to normal fetch–decode– execute status when the interrupt handler is finished. A machine language is a list of binary numbers representing executable machine instructions, assembly language program uses symbolic instructions to represent the numerical data from which the machine language program is derived. does not offer a large variety of data types or instructions for the programmer. programs represent a lower-level method of programming. assembler is one step in the process of converting source code into the machine can understand.