CA module 2 pdf[2].pdf

1 MEMORY ARCHITECTURE Module 2  2 CONTENTS  Memory Hierarchy  RAM- Structure of RAM cell, Organization of a RAM cell  DRAM  SRAM  ROM.  Cache memory  Mapping techniques  V...

1 MEMORY ARCHITECTURE Module 2  2 CONTENTS  Memory Hierarchy  RAM- Structure of RAM cell, Organization of a RAM cell  DRAM  SRAM  ROM.  Cache memory  Mapping techniques  Virtual memory  Address translation.  3 MEMORY  Computer data storage refers to computer components, devices and recording media that retain digital data used for computing for some interval of time.  Computer data storage provides one of the core functions of modern computers ie, Information Retention.  So far, no practical universal storage medium exists, and all forms of storage have some drawbacks.  So computer system usually contains several kinds of storage, each with an individual purpose.  4 MEMORY CHARACTERISTICS  The complex subject computer memory can be made manageable by classifying the memory systems according to their key characteristics.  The most important characteristics are Memory type & memory size Memory location Word length ( the number of bits actually stored or retrieved in one memory access) Addressable unit Unit of transfer ( for main memory it is word, for external memory it is blocks) Access method ( random access, direct access, serial access memories) Performance and cost ( access time: average time to perform read / write operation) Physical type Physical characteristics ( destructive & non destructive, dynamic & static, volatile and non volatile) Memory cycle time ( access time + any additional time required)  5 Some basic concepts  Maximum size of the Main Memory CPU-Main Memory Connection Processor Memory k-bit address bus MAR n-bit data bus Up to 2 k addressable MDR locations Word length = n bits Control lines ( R / W, MFC, etc.)  6 THE MEMORY SYSTEM SEMICONDUCTOR RAM MEMORIES  7 Internal organization of memory chips  Each memory cell can hold one bit of information.  Memory cells are organized In the form of an array.  One row is one memory word.  All cells of a row are connected to a common line, known as the “word line”.  Word line is connected to the address decoder.  Sense/write circuits are connected to the data input/output lines of the memory chip. Internal Organization Of Memory Chips 8  9 Organization of a 1Kx 1 memory chip  10 Contd..  DYNAMIC RAM’S (DRAMs): Do not retain their state indefinitely. Contents must be periodically refreshed. Information is stored in DRAM cell in the form of a charge on a capacitor (that is maintained for only tens of milliseconds). Since the cell is required to store information for a much longer time, its contents must be periodically refreshed by restoring the capacitor charge to its full value.  11 DRAM Cell  To store information in this cell, transistor T is turned ON and an appropriate voltage is applied to the bit line.  This cause a known amount of charge to be stored in the capacitor.  After the charge is turned OFF, the capacitor begins to discharge  This is caused by capacitors own leakage resistance and the transistor continues to conduct a tiny amount of current, after it is turned OFF  Hence, information stored in the cell can be retrieved correctly only if it is read before the charge on the capacitor drops below some threshold value  12 Contd..  During a read operation, the transistor in the selected cell is turned ON  A sense amplifier connected to the bit line detect whether the charge stored on the capacitor is above the threshold value.  If so, it drives the bit line to a full voltage that represents logic 1.  This voltage recharges the capacitor to full charge that correspond to logic value 1.  If the sense amplifier detects that the charge on the capacitor is below the threshold value, it pulls the bit line to ground level, which ensures that the capacitor will have no charge, representing logic value 0  Thus reading the contents of the cell automatically refreshes its contents  13 Synchronous and Asynchronous DRAMs Asynchronous DRAM: Asynchronous DRAM (Dynamic Random-Access Memory) is a type of DRAM where the memory access operations are not coordinated with the system clock. The CPU sends control signals directly to the DRAM, and the memory responds as quickly as it can. The timing of operations is determined by the DRAM’s internal circuitry rather than an external clock. Generally slower compared to synchronous DRAM because it operates independently of the system clock. The access time depends on the DRAM itself, which can lead to delays if the memory is not ready when the CPU requests data. Typically used in systems where cost is a primary concern and speed is less critical. It was common in earlier computing systems.  14 Contd.. Synchronous DRAM (SDRAM): Synchronous DRAM is a type of DRAM that operates in sync with the system clock, meaning all operations are coordinated with the CPU's clock signal. The memory performs tasks in precise steps, aligned with the clock cycles. This synchronization allows for more predictable performance and efficient data transfer. Faster than asynchronous DRAM because it can transfer data more efficiently by reducing wait times. SDRAM can handle bursts of data and is capable of processing multiple instructions per clock cycle. Widely used in modern computing systems, including PCs, servers, and other high-performance applications where speed and efficiency are critical.  15 Contd.. Synchronous DRAM Asynchronous DRAM (SDRAM)  Not synchronized with the system clock  Synchronized with the system clock  Controlled by internal DRAM circuitry;  Controlled by the external system clock independent of the clock  Faster, as operations are timed with the  Slower, as operations are not aligned clock cycle with the system clock  More efficient; can handle bursts of data  Less efficient; dependent on the dram’s transfer readiness  More complex, with precise timing  Simpler design, less complex timing aligned with the clock requirements  Lower latency due to coordinated  Higher latency due to lack of operations with the clock synchronization  Modern systems where performance is  Earlier systems or cost-sensitive critical applications  More predictable and reliable  Less predictable performance performance  16 STATIC RAM’S (SRAMs): Consist of circuits that are capable of retaining their state as long as the power is applied. Volatile memories, because their contents are lost when power is interrupted. Access times of static RAMs are in the range of few nano seconds. However, the cost is usually high. SRAMs are fast  17 SRAM Cell  Two transistor inverters are cross connected to implement a basic flip-flop.  The cell is connected to one word line and two bits lines by transistors T1 and T2  When word line is at ground level, the transistors are turned off and the latch retains its state  Read operation: In order to read state of SRAM cell, the word line is activated to close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of b and b’  18 Memory System Considerations The choice of RAM chip for a given application depends on : Cost Speed Power Dissipation Size of Chip  19 Read-Only Memories (ROMs)  SRAM and SDRAM chips are volatile (Lose the contents when the power is turned off. )  Many applications need memory devices to retain contents after the power is turned off.  Non-volatile memory is read in the same manner as volatile memory.  Separate writing process is needed to place information in this memory.  Normal operation involves only reading of data, this type of memory is called Read-Only memory (ROM).  20.  21 READ-ONLY MEMORIES (CONTD.,)  Read-Only Memory: Data are written into a ROM when it is manufactured.  Programmable Read-Only Memory (PROM): Allow the data to be loaded by a user. Process of inserting the data is irreversible. Storing information specific to a user in a ROM is expensive. Providing programming capability to a user may be better.  Erasable Programmable Read-Only Memory (EPROM): Stored data to be erased and new data to be loaded. Flexibility, useful during the development phase of digital systems. Erasable, reprogrammable ROM. Erasure requires exposing the ROM to UV light.  22 Read-Only Memories (Contd.,)  Electrically Erasable Programmable Read-Only Memory (EEPROM): To erase the contents of EPROMs, they have to be exposed to ultraviolet light. Physically removed from the circuit. EEPROMs the contents can be stored and erased electrically.  Flash memory Has similar approach to EEPROM. Read the contents of a single cell, but write the contents of an entire block of cells. Flash devices have greater density. Higher capacity and low storage cost per bit. Power consumption of flash memory is very low, making it attractive for use in equipment that is battery-driven. Single flash chips are not sufficiently large, so larger memory modules are implemented using flash cards and flash drives.  23 SPEED, SIZE AND COST  A big challenge in the design of a computer system is to provide a sufficiently large memory, with a reasonable speed at an affordable cost.  Static RAM: Very fast, but expensive, because a basic SRAM cell has a complex circuit making it impossible to pack a large number of cells onto a single chip.  Dynamic RAM: Simpler basic cell circuit, hence are much less expensive, but significantly slower than SRAMs.  Magnetic disks: Storage provided by DRAMs is higher than SRAMs, but is still less than what is necessary. Secondary storage such as magnetic disks provide a large amount of storage, but is much slower than DRAMs.  24 MEMORY HIERARCHY  Fastest access is to the data held in 25at Processor processor registers. Registers are Registers the top of the memory hierarchy. Increasing Increasing Increasing speed cost per bit Relatively small amount of memory size Primary L1 that can be implemented on the cache processor chip. This is processor cache. Two levels of cache. Level 1 (L1) cache is on the processor chip. Level 2 Secondary (L2) cache is in between main memory cache L2 and processor. Next level is main memory, implemented as SIMMs. Much larger, Main but much slower than cache memory. memory Next level is magnetic disks. Huge amount of inexpensive storage. Speed of memory access is critical, the Magnetic disk idea is to bring instructions and data secondary memory that will be used in the near future as close to the processor as possible.  26 The Memory System CACHE MEMORIES  27 Cache Memories Processor is much faster than the main memory. ✓ As a result, the processor has to spend much of its time waiting while instructions and data are being fetched from the main memory. ✓ Major obstacle towards achieving good performance. Speed of the main memory cannot be increased beyond a certain point. Cache memory is an architectural arrangement which makes the main memory appear faster to the processor than it really is. Cache memory is based on the property of computer programs known as “locality of reference”. Processor Cache Main memory  28 Locality of Reference Analysis of programs indicates that many instructions in localized areas of a program are executed repeatedly during some period of time, while the others are accessed relatively less frequently. These instructions may be the ones in a loop, nested loop or few procedures calling each other repeatedly. This is called “Locality Of Reference” Temporal locality of reference: Recently executed instruction is likely to be executed again very soon. Spatial locality of reference: Instructions with addresses close to a recently instruction are likely to be executed soon.  29 Cache memories Processor issues a Read request, a block of words is transferred from the main memory to the cache, one word at a time. Subsequent references to the data in this block of words are found in the cache. At any given time, only some blocks in the main memory are held in the cache. Which blocks in the main memory are in the cache is determined by a “MAPPING FUNCTION”. When the cache is full, and a block of words needs to be transferred from the main memory, some block of words in the cache must be replaced. This is determined by a “REPLACEMENT ALGORITHM”.  30 Cache hit Existence of a cache is transparent to the processor. The processor issues Read and Write requests in the same manner. If the data is in the cache it is called a Read or Write hit. Read hit: The data is obtained from the cache. Write hit: ✓ Cache has a replica of the contents of the main memory. ✓ Contents of the cache and the main memory may be updated simultaneously. This is the write-through protocol. ✓ Update the contents of the cache, and mark it as updated by setting a bit known as the dirty bit or modified bit. The contents of the main memory are updated when this block is replaced. This is write-back or copy-back protocol.  31 Cache miss If the data is not present in the cache, then a Read miss or Write miss occurs. Read miss: ▪ Block of words containing this requested word is transferred from the memory. ▪ After the block is transferred, the desired word is forwarded to the processor. ▪ The desired word may also be forwarded to the processor as soon as it is transferred without waiting for the entire block to be transferred. This is called load-through or early-restart. Write-miss: ▪ Write-through protocol is used, then the contents of the main memory are updated directly. ▪ If write-back protocol is used, the block containing the addressed word is first brought into the cache. The desired word is overwritten with new information.  32 Cache Coherence Problem A bit called as “valid bit” is provided for each block. If the block contains valid data, then the bit is set to 1, else it is 0. Valid bits are set to 0, when the power is just turned on. When a block is loaded into the cache for the first time, the valid bit is set to 1. Data transfers between main memory and disk occur directly bypassing the cache. When the data on a disk changes, the main memory block is also updated. However, if the data is also resident in the cache, then the valid bit is set to 0. What happens if the data in the disk and main memory changes and the write-back protocol is being used? In this case, the data in the cache may also have changed and is indicated by the dirty bit. The copies of the data in the cache, and the main memory are different. This is called the cache coherence problem. One option is to force a write-back before the main memory is updated from the disk.  33 Mapping functions Mapping functions determine how memory blocks are placed in the cache. Three mapping functions: o Direct mapping o Associative mapping oSet-associative mapping. A simple processor example: o Cache consisting of 128 blocks of 16 words each. o Total size of cache is 2048 (2K) words. o Main memory is addressable by a 16-bit address. o Main memory has 64K words. o Main memory has 4K blocks of 16 words each.  34 Direct mapping  35 Contd… Block j of the main memory maps to j modulo 128 of the cache. 0 maps to 0, 129 maps to 1. More than one memory block is mapped onto the same position in the cache. May lead to contention for cache blocks even if the cache is not full. Resolve the contention by allowing new block to replace the old block, leading to a trivial replacement algorithm. Memory address is divided into three fields: - Low order 4 bits determine one of the 16 words in a block. - When a new block is brought into the cache, the next 7 bits determine which cache block this new block is placed in. - High order 5 bits determine which of the possible 32 blocks is currently present in the cache. These are tag bits. Simple to implement but not very flexible.  36 Associative mapping  37 Contd… Main memory block can be placed into any cache position. Memory address is divided into two fields: o Low order 4 bits identify the word within a block. o High order 12 bits or tag bits identify a memory block when it is resident in the cache. Flexible, and uses cache space efficiently. Replacement algorithms can be used to replace an existing block in the cache when the cache is full. Cost is higher than direct-mapped cache because of the need to search all 128 patterns to determine whether a given block is in the cache.  38 Set-Associative mapping  39 Blocks of cache are grouped into sets. Mapping function allows a block of the main memory to reside in any block of a specific set. Divide the cache into 64 sets, with two blocks per set. Memory block 0, 64, 128 etc. map to block 0, and they can occupy either of the two positions. Memory address is divided into three fields: o 6 bit field determines the set number. o High order 6 bit fields are compared to the tag fields of the two blocks in a set. Set-associative mapping combination of direct and associative mapping. Number of blocks per set is a design parameter. o One extreme is to have all the blocks in one set, requiring no set bits (fully associative mapping). o Other extreme is to have one block per set, is the same as direct mapping.  40 Performance considerations  A key design objective of a computer system is to achieve the best possible performance at the lowest possible cost. Price/performance ratio is a common measure of success.  Performance of a processor depends on: How fast machine instructions can be brought into the processor for execution. How fast the instructions can be executed.  41 The Memory System VIRTUAL MEMORY Virtual Memories  Recall that an important challenge in the design of a computer system is to provide a large, fast memory system at an affordable cost.  Architectural solutions to increase the effective speed and size of the memory system.  Cache memories were developed to increase the effective speed of the memory system.  Virtual memory is an architectural solution to increase the effective size of the memory system. 42 Contd.. Recall that the addressable memory space depends on the number of address bits in a computer. For example, if a computer issues 32-bit addresses, the addressable memory space is 4G bytes. Physical main memory in a computer is generally not as large as the entire possible addressable space. Physical memory typically ranges from a few hundred megabytes to 1G bytes. Large programs that cannot fit completely into the main memory have their parts stored on secondary storage devices such as magnetic disks. Pieces of programs must be transferred to the main memory from secondary storage before they can be executed. 43 Contd..  When a new piece of a program is to be transferred to the main memory, and the main memory is full, then some other piece in the main memory must be replaced. Recall this is very similar to what we studied in case of cache memories.  Operating system automatically transfers data between the main memory and secondary storage.  Application programmer need not be concerned with this transfer.  Also, application programmer does not need to be aware of the limitations imposed by the available physical memory. 44  Contd..  Techniques that automatically move program and data between main memory and secondary storage when they are required for execution are called virtual-memory techniques.  Programs and processors reference an instruction or data independent of the size of the main memory.  Processor issues binary addresses for instructions and data. These binary addresses are called logical or virtual addresses.  Virtual addresses are translated into physical addresses by a combination of hardware and software subsystems.  If virtual address refers to a part of the program that is currently in the main memory, it is accessed immediately.  If the address refers to a part of the program that is not currently in the main memory, it is first transferred to the main memory before it can be used. 45 Virtual Memory Organization Memory management unit (MMU) translates Virtual addresses into physical addresses. If the desired data or instructions are in the Main memory they are fetched as described previously. If the desired data or instructions are not in the main memory, they must be transferred from secondary storage to the main memory. MMU causes the operating system to bring the data from the secondary storage into the main memory. 46  Address Translation Assume that program and data are composed of fixed-length units called pages. A page consists of a block of words that occupy contiguous locations in the main memory. Page is a basic unit of information that is transferred between secondary storage and main memory. Size of a page commonly ranges from 2k to 16k bytes. Pages should not be too small, because the access time of a secondary storage device is much larger than the main memory. Pages should not be too large, else a large portion of the page may not be used, and it will occupy valuable space in the main memory. 47 Contd..  Concepts of virtual memory are similar to the concepts of cache memory.  Cache memory: o Introduced to bridge the speed gap between the processor and the main memory. o Implemented in hardware.  Virtual memory: o Introduced to bridge the speed gap between the main memory and secondary storage. o Implemented in part by software. 48  Contd.. Each virtual or logical address generated by a processor is interpreted as a virtual page number (high-order bits) plus an offset (low-order bits) that specifies the location of a particular byte within that page. Information about the main memory location of each page is kept in the page table. o Main memory address where the page is stored. oCurrent status of the page. Area of the main memory that can hold a page is called as page frame. Starting address of the page table is kept in a page table base register. 49 Contd.. Virtual page number generated by the processor is added to the contents of the page table base register. This provides the address of the corresponding entry in the page table. The contents of this location in the page table give the starting address of the page if the page is currently in the main memory. 50 51  Contd.. Page table entry for a page also includes some control bits which describe the status of the page while it is in the main memory. One bit indicates the validity of the page. Indicates whether the page is actually loaded into the main memory. Allows the operating system to invalidate the page without actually removing it. One bit indicates whether the page has been modified during its residency in the main memory. This bit determines whether the page should be written back to the disk when it is removed from the main memory. Similar to the dirty or modified bit in case of cache memory.  Other control bits for various other types of restrictions that may be imposed.  For example, a program may only have read permission for a page, but not write or modify permissions. 52  Contd.. Where should the page table be located? Recall that the page table is used by the MMU for every read and write access to the memory. Ideal location for the page table is within the MMU. Page table is quite large. MMU is implemented as part of the processor chip. Impossible to include a complete page table on the chip. Page table is kept in the main memory. A copy of a small portion of the page table can be accommodated within the MMU. Portion consists of page table entries that correspond to the most recently accessed pages. 53  Contd.. A small cache called as Translation Lookaside Buffer (TLB) is included in the MMU. TLB holds page table entries of the most recently accessed pages. Recall that cache memory holds most recently accessed blocks from the main memory. Operation of the TLB and page table in the main memory is similar to the operation of the cache and main memory. Page table entry for a page includes: Address of the page frame where the page resides in the main memory. Some control bits. In addition to the above for each page, TLB must hold the virtual page number for each page. 54 55  56 Contd.. Associative-mapped TLB High-order bits of the virtual address generated by the processor select the virtual page. These bits are compared to the virtual page numbers in the TLB. If there is a match, a hit occurs and the corresponding address of the page frame is read. If there is no match, a miss occurs and the page table within the main memory must be consulted. Set-associative mapped TLBs are found in commercial processors. Contd..  How to keep the entries of the TLB coherent with the contents of the page table in the main memory?  Operating system may change the contents of the page table in the main memory.  Simultaneously it must also invalidate the corresponding entries in the TLB.  A control bit is provided in the TLB to invalidate an entry.  If an entry is invalidated, then the TLB gets the information for that entry from the page table.  Follows the same process that it would follow if the entry is not found in the TLB or if a “miss” occurs. 57  Contd.. What happens if a program generates an access to a page that is not in the main memory? In this case, a page fault is said to occur. Whole page must be brought into the main memory from the disk, before the execution can proceed. Upon detecting a page fault by the MMU, following actions occur: o MMU asks the operating system to intervene by raising an exception. o Processing of the active task which caused the page fault is interrupted. o Control is transferred to the operating system. o Operating system copies the requested page from secondary storage to the main memory. o Once the page is copied, control is returned to the task which was interrupted. 58  Contd.. Servicing of a page fault requires transferring the requested page from secondary storage to the main memory. This transfer may incur a long delay. While the page is being transferred the operating system may: o Suspend the execution of the task that caused the page fault. o Begin execution of another task whose pages are in the main memory. Enables efficient use of the processor. 59  Contd.. When a new page is to be brought into the main memory from secondary storage, the main memory may be full. Some page from the main memory must be replaced with this new page. How to choose which page to replace? o This is similar to the replacement that occurs when the cache is full. o The principle of locality of reference (?) can also be applied here. o A replacement strategy similar to LRU can be applied. Since the size of the main memory is relatively larger compared to cache, a relatively large amount of programs and data can be held in the main memory. o Minimizes the frequency of transfers between secondary storage and main memory. 60