AVR Memories.pdf

‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ Lecture 3 AVR Memories Page 1  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ In this part we will describe the different memories in the ATmega328P. The AVR architecture has two main me...

‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ Lecture 3 AVR Memories Page 1  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ In this part we will describe the different memories in the ATmega328P. The AVR architecture has two main memory spaces, the data memory and the program memory space. In addition, the ATmega328P features an EEPROM memory for data storage. Reprogrammable Flash Program Memory The ATmega328P contains 32Kbytes on-chip reprogrammable flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the flash is organized as 16K × 16. The ATmega328P program counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. In ATmega328P, the flash program memory space is organized into two sections (Figure 1): 1- Boot Loader Section. 2- Application Program Section. Figure 1: ATmega328P Flash Program Memory The application section is the section of the flash that is used for storing the application code. The application section can never store any boot loader code. The boot loader is a small program that has been loaded on to the microcontroller. It allows you to upload code into the application section. The boot loader program use any available data interface protocol to read code (from the computer) and write that code into the flash memory of the microcontroller. So first if you were to do anything on those microcontrollers you need a boot loader burned on those chips. Note the ATmega328p microcontroller cannot be used with the Arduino IDE until it is flashed with the Arduino boot loader, and that is why boot loader comes programmed on the microcontrollers on Arduino boards. The boot loader performs two tasks: 1- It monitors the serial communication line to see if the computer is trying to send (upload) a program code. If this is the case, it accepts the code from the computer and stores it in the application section of the flash program memory. 2- When the computer is not trying to upload new code to the microcontroller, the boot loader instructs the chip to run the code that is already stored in the program memory. Once it runs your program, the Arduino continuously loops through the program and does as long as the board has power. Page 2  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ The boot loader program must be located in the Boot Loader Section (BLS). The code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. The boot loader can thus even modify itself (update itself), and it can also erase itself (if the boot loader is no longer needed after uploading the application code and no updates are expected, it can erase itself). The size of the different sections is configured by the BOOTSZ fuses as shown in the Figure 2 below. Figure 2: Program memory sections with different sizes Table 1 shows different BOOTSZ fuse configurations. Boot Reset End Address Boot Application Boot Loader BOOTSZ1 BOOTSZ0 Pages Application (Start Size Flash Section Flash Section Section Boot Loader Section) 256 1 1 4 0x0000-0x3EFF 0x3F00-0x3FFF 0x3EFF 0x3F00 words 512 1 0 8 0x0000-0x3DFF 0x3E00-0x3FFF 0x3DFF 0x3E00 words 1024 0 1 16 0x0000-0x3BFF 0x3C00-0x3FFF 0x3BFF 0x3C00 words 2048 0 0 32 0x0000-0x37FF 0x3800-0x3FFF 0x37FF 0x3800 words Table 1: Boot Size Configuration in ATmega328P =========================================================================================== One question that we must ask about any microcontroller (or microprocessor) is: At what address does the CPU wake up when power is applied? By powering up we mean applying Vcc to the RESET pin. Each microprocessor is different. In the case of the AVR microcontrollers, when the microcontroller is powered up it wakes up at memory address 0x0000 of the flash memory. In other words, when the AVR is powered up, the PC (program counter) has the value of 0x0000 in it. =========================================================================================== Page 3  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ THE AVR DATA MEMORY (SRAM) As we mentioned previously, in AVR microcontrollers there are two kinds of memory space: program memory space and data memory space. Our program code is stored in program memory space, whereas the data memory stores data. In the following, we will discuss the data memory space. Figure 3 shows how the ATmega328P SRAM memory is organized. The data memory is composed of three parts: 1- General purpose registers (GPRs). 2- I/O memory. 3- Internal SRAM. Figure 3: Data Memory Map There are 2304 data memory locations (02303) (0x0000 – 0x08FF). - The first 32 locations (0x0000-0x001F) address the register file. - The next 64 locations (0x0020-0x005F) address the standard I/O memory. - Then 160 locations (0x0060-0x00FF) address of extended I/O memory. - And the next 2048 locations address the internal data SRAM (0x100-0x08FF). The five different addressing modes for the data memory cover: Direct, indirect with displacement, indirect, indirect with pre-decrement, and indirect with post-increment. We will discuss these addressing modes later in the next lecture. GPRs (General Purpose Registers) As we discussed previously, the GPRs use 32 bytes of data memory space. They always take the address location 00-1F in the data memory space. Details of the GPRs were discussed in the previous lecture (AVR CPU). ================================================================= Page 4  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ I/O memory  64 I/O Registers In addition to the general purpose registers (GPRs), the data memory contains 64 I/O registers within the address range 0x20 - 0x5F in SRAM (0x00-0x3F in I/O address space). Each I/O register in the I/O memory space is made of 8-bit register. - This memory space contains the PINx, PORTx, and DDRx registers, as well as the status register (SREG) and Timer interrupt flag registers (TIFR0, TIFR1, and TIFR2), external interrupts …. - These I/O registers can be directly addressed using assembly instructions. IN R16, PINB ; Read data from port B and put in R16 - I/O specific commands IN and OUT are used with I/O registers within the address range 0x20 - 0x5F in SRAM (0x00-0x3F in I/O address space). OUT DDRB, R16 - The first 32 I/O registers within the address range 0x20 - 0x3F in SRAM (0x00- 0x1F in I/O address space) are: o Directly bit-accessible using the SBI and CBI instructions. For example: SBI PORTC, 0 ; Set bit no. 0 in Port C register (PC0=1) o In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. For example: SBIC EECR, EEPE ; SBIC means Skip next instruction if EEPE bit in EECR IO register is cleared (=0) o The status register (SREG) is located in the SRAM address 0x5F. o The CBI and SBI instructions work only within the memory address space (0x20 - 0x3F in SRAM) which means it works only with the first 32 I/O registers (0x00-0x1F in I/O memory).  160 Extended I/O Registers There are additional 160 extended I/O registers within the address range 0x60 - 0xFF in SRAM that control all of the other peripheral features of the ATmega328P, including serial communication, interrupts, timer / counters, ADC, and more. For the extended I/O space only the ST/STS/STD and LD/LDS/LDD instructions can be used.  3 General Purpose I/O Registers The ATmega328P contains three general purpose I/O registers (Figure 4). - GPIOR0 General purpose I/O register 0 (on the SRAM address 0x3E) - GPIOR1 General purpose I/O register 1 (on the SRAM address 0x4A) - GPIOR2 General purpose I/O register 2 (on the SRAM address 0x4B) Page 5  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers within the address range 0x20 - 0x3F in SRAM (0x00-0x1F in I/O address space) are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions, which means that only GPIOR0 can be used with these instructions. Figure 4: Three general purpose I/O registers in ATmega328P ================================================================================== Internal data SRAM The remaining data space is used to store variable data in memory, as well as to house the stack. Each location of the SRAM can be accessed directly by its address. Each location is 8 bits wide and can be used to store any data. The internal data SRAM access is performed in two clkCPU cycles as described below in Figure 5. Figure 5: On-chip Data SRAM Access Cycles ================================================================= Page 6  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ EEPROM Data Memory As we mentioned previously, the data in SRAM will be lost if the power is disconnected. However, we need a place to save our data in a separate data space from SRAM to protect them against power failure. So in addition to the volatile SRAM data space, non-volatile EEPROM is used to save data that can be changed but should remain stored in memory even in the absence of power to the device. The AVR ATmega328P contains 1Kbyte of non-volatile data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. Since ATmega328P has 1Kbyte (1024 byte) EEPROM locations, we need 10 bits to address each location in EEPROM space. ================================================================= EEPROM Registers There are three I/O registers that are directly related to EEPROM. These registers are: 1- EEPROM Data Register (EEDR). 2- EEPROM Address Register High-Low (EEARH-EEARL). 3- EEPROM Control Register (EECR). The EEPROM registers are accessible in the I/O space. Each of the EEPROM registers is discussed in detail below. ================================================================= 1- EEPROM Data Register (EEDR): Figure 6 demonstrates the EEPROM data register. Figure 6: EEDR Register EEDR Bits 7...0: For the EEPROM write operation, to write data to EEPROM, the CPU have to write it firstly to the EEDR register and then it will transfer to EEPROM in the address given by the EEAR register. For the EEPROM read operation, to read data from EEPROM, the CPU have to read from EEDR the data read out from the EEPROM at the address given by EEAR. In other words, EEDR is a bridge between EEPROM and CPU. ================================================================= Page 7  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ 2- EEPROM Address Register (EEARH and EEARL) Figure 7 demonstrates the EEPROM address register. Figure 7: EEARH:EEARL Register When you want to read from or write to EEPROM, you should first load the EEPROM location address in the EEPROM address register. The EEARH:EEARL registers together make a 16-bit register, and because ATmega328P has 1 Kbyte EEPROM locations, we need only 10 bits to address each location in EEPROM space. These bits are EEAR0 – EEAR9. The bits 10–15 are reserved bits in the AVR ATmega328P and will always read as 0. ================================================================= 3- EEPROM Control Register (EECR) The EECR register (Figure 8) is used to select the kind of operation to perform on. Figure 8: EECR Register Bits 7...6 – (Reserved Bits): These bits are reserved bits in the ATmega328P and will always read as zero. Bits 5, 4 – EEPROM Programming Mode Bits (EEPM1 and EEPM0): These bits define which programming action that will be triggered when writing EEPE bit to 1. It is possible to: - Erase the old data value and write the new value in one operation, or - Split the erase and write operations in two different operations. The programming times for the different modes are shown in Table 2. EEPM1 EEPM0 Programming time Operation 0 0 3.4 ms Erase and write in one operation 0 1 1.8 ms Erase only 1 0 1.8 ms Write only 1 1 ------ Reversed for future use Table 2: EEPROM Mode Bits Notice that while EEPE is set, any write to EEPMn will be ignored. Page 8  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ Bit 3 – EERIE: EEPROM Ready Interrupt Enable - Writing EERIE to one enables the EEPROM interrupt if I bit in SREG is set. - Writing EERIE to zero disables the interrupt. The EEPROM ready interrupt generates an interrupt when EEPE is cleared. The interrupt will not be generated during EEPROM write (when EEPE=1). Bit 2 – EEMPE: EEPROM Master Write Enable - When EEMPE is set (EEMPE=1), setting EEPE within four clock cycles will write data to the EEPROM at the selected address. - If EEMPE is zero (EEMPE=0), setting EEPE will have no effect. Note: when EEMPE has been written to 1 by software, hardware clears it (EEMPE=0) after 4 clock cycles. This prevents unwanted write operations on EEPROM contents. Bit 1 – EEPE: EEPROM Write Enable The EEPE bit is the write strobe to the EEPROM. - When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit (Bit2) must be written to one before a logical one is written to EEPE; otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is not essential): 1- Wait until EEPE becomes zero. 2- Write EEPROM address to EEAR. 3- Write EEPROM data to EEDR. 4- Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR. 5- Within four clock cycles after setting EEMPE, write a logical one to EEPE. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. Bit 0 – EERE: EEPROM Read Enable The EEPROM read enable signal EERE is the read strobe to the EEPROM. - When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. Notice that we cannot start read or write operations before the last write operation is finished (wait until EEPE=0). So, the user should poll the EEPE bit before starting a new read or write operation.  If EEPE is zero, it means that EEPROM is ready to start a new read or write operation. Page 9  ‫ هــــدى جمعــــه‬.‫ د‬/‫إعداد‬ The following procedure should be followed when reading from the EEPROM (the order of steps 2 and 3 is not essential): 1- Wait until EEPE becomes zero. 2- Write new EEPROM address to EEAR. 3- Set the EERE bit to one. 4- Read EEPROM data from EEDR. ================================================================================== Example: Write assembly program to store 'A' into location 0x015C of EEPROM. Solution: WAIT: ; Wait for last write to finish SBIC EECR, EEPE ; Check EEPE bit to see if last write operation is finished ; SBIC Skip next instruction if EEPE bit in EECR IO register is cleared (=0) RJMP WAIT ; wait more LDI R18, 0x01 ; Load high byte of address to R18 LDI R17, 0x5C ; Load low byte of address to R17 OUT EEARH, R18 ; Load high byte of address to EEARH OUT EEARL, R17 ; Load low byte of address to EEARL LDI R16, 'A' ; Load 'A' to R16 OUT EEDR, R16 ; Load R16 to EEPROM Data Register SBI EECR, EEMPE ; Set EEPROM Master Write Enable to 1 SBI EECR, EEPE ; Set EEPROM Write Enable to 1 ================================================================= Example: Write assembly code to read the content of location 0x02B1 of EEPROM. Solution: WAIT: ; Wait for last write to finish SBIC EECR, EEPE ; Check EEPE bit to see if last write operation is finished ; SBIC Skip next instruction if EEPE bit in EECR IO register is cleared (=0) RJMP WAIT ; wait more LDI R18, 0x02 ; Load high byte of address to R18 LDI R17, 0xB1 ; Load low byte of address to R17 OUT EEARH, R18 ; Load high byte of address to EEARH OUT EEARL, R17 ; Load low byte of address to EEARL SBI EECR, EERE ; Set Read Enable to one IN R16, EEDR ; Load EEPROM Data Register to R16 ================================================================= SRAM vs. EEPROM in AVR chips EEPROM does not lose its data when power is off, whereas SRAM does. So, the EEPROM is used for storing data that should rarely be changed and should not be lost when the power is off; whereas the SRAM is used for storing data and parameters that are changed frequently. ================================================================= Page 10