Combinational and Sequential Circuits - PDF

## Combinational and Sequential Circuits **1. Explain the differences between Combinational and Sequential Circuits with their block diagrams and examples.** **Feature** | **Combinational Circuit** | **Sequential Circuit** --- | --- | --- **Definition** | Output depends only on the present inputs....

## Combinational and Sequential Circuits **1. Explain the differences between Combinational and Sequential Circuits with their block diagrams and examples.** **Feature** | **Combinational Circuit** | **Sequential Circuit** --- | --- | --- **Definition** | Output depends only on the present inputs. | Output depends on both current inputs and past inputs (memory). **Memory** | No memory elements. | Requires memory elements (e.g., flip-flops or latches). **Speed** | Faster, as there are no memory elements or feedback loops. | Slower, as feedback and memory introduce delays. **Output** | A function of only the present inputs. | A function of the current inputs and previous outputs or states. **Design Complexity** | Simpler, as it does not involve memory. | More complex, as it needs memory and feedback mechanisms. **Usage** | Used for basic operations like addition, selection, and data encoding/decoding. | Used in systems that require state retention, such as counters, registers, and state machines. **Example Components** | Multiplexers, Adders, Decoders. | Flip-flops, Counters, Shift Registers. **Block diagram of combinational circuit**: - A block diagram shows a combinational circuit with n inputs, a combinational circuit box, and m outputs. **Block diagram of sequential circuit**: - A block diagram shows a sequential circuit with n inputs, a combinational circuit box, memory elements, and m outputs. ## Encoder **2. Define Encoder. Design a Four-input Priority Encoder.** An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. - A priority encoder is an encoder circuit that includes the priority function. - The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. **Truth Table of a Priority Encoder:** **Inputs** | **Outputs** ---|---| Do | D1 | D2 | D3 | X | Y | V 0 | 0 | 0 | 0 | X | X | 0 1 | 0 | 0 | 0 | 0 | 0 | 1 0 | 1 | 0 | 0 | 0 | 1 | 1 0 | 0 | 1 | 0 | 1 | 0 | 1 0 | 0 | 0 | 1 | 1 | 1 | 1 - In addition to the two outputs x and y, the circuit has a third output designated by V; this is a valid bit indicator that is set to 1 when one or more inputs are equal to 1. - If all inputs are 0, there is no valid input and V is equal to 0. The other two outputs are not inspected when V equals 0 and are specified as don’t-care conditions. - Input D3 has the highest priority, so, regardless of the values of the other inputs, when this input is 1, the output for xy is 11 (binary 3). - D2 has the next priority level. The output is 10 if D2 = 1, provided that D3 = 0, regardless of the values of the other two lower priority inputs. The output for D1 is generated only if higher priority inputs are 0. **Four-input priority encoder**: - A diagram shows a four-input priority encoder implemented using logic gates. ## Verilog **3. Write the Verilog program to Implement Full Adder and Subtractor Circuits.** **Full Adder** ``` module full_adder( input A, // First input bit input B, // Second input bit input Cin, // Carry-in output Sum, // Sum output output Cout // Carry-out output ); assign Sum = A ^ B ^ Cin; // Sum = A XOR B XOR Cin assign Cout = (A & B) | (B & Cin) | (A & Cin); // Cout = (A AND B) OR (B AND Cin) OR (A AND Cin) endmodule ``` **Full Subtractor** ``` module full_subtractor( input A, // Minuend bit input B, // Subtrahend bit input Bin, // Borrow-in output Diff,// Difference output output Bout // Borrow-out output ); assign Diff = A^B^ Bin; // Difference = A XOR B XOR Bin assign Bout = (~A & B) | ((~A | B) & Bin); // Bout = (NOT A AND B) OR ((NOT A OR B) AND Bin) endmodule ``` ## Flip-flops **4. Write the Characteristic Table and Equations of SR, JK, D and T Flip Flops.** **SR Latch:** - **SR Latch with nor gates:** - A table showing inputs and outputs for SR Latch with NOR gates. - **SR Latch with NAND gates:** - A table showing inputs and outputs for SR Latch with NAND gates. - **SR Latch with control input:** - A table showing inputs and outputs for an SR Latch with a control input. - **Function table:** - A table showing the function table for SR Latch. **JK Flip-Flop:** - A table showing inputs and outputs for a JK Flip-Flop. **D Flip-Flop:** - A table showing inputs and outputs for a D Flip-Flop. **T Flip-Flop:** - A table showing inputs and outputs for a T Flip-Flop. **Characteristic equation:** - **T FF:** - A table showing inputs and outputs for a T Flip-Flop as well as a diagram with the inputs and outputs. - **DFF:** - A table showing inputs and outputs for a D Flip-Flop as well as a diagram with the inputs and outputs. - **JKFF:** - A table showing inputs and outputs for a JK Flip-Flop as well as a diagram with the inputs and outputs. ## Dataflow Modeling **5. Explain Dataflow Modeling in Verilog with an example program.** Dataflow modeling is used mostly for describing the Boolean equations of combinational logic. - Dataflow modeling uses continuous assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a net. The data type family net is used in Verilog HDL to represent a physical connection between circuit elements. **HDL Example 4.3 (Dataflow: Two-to-Four Line Decoder)** ``` // Dataflow description of two-to-four-line decoder // See Fig. 4.19. Note: The figure uses symbol E, but the // Verilog model uses enable to clearly indicate functionality. module decoder_2x4_df ( // Verilog 2001, 2005 syntax output [0: 3] D, input A, B, enable ); assign D[0] = !((!A) && (!B) && (!enable)), D[1] = !(*!A) && B && (!enable)), D[2] = !(A && B && (!enable) D[3] = !(A && B && (!enable)) endmodule ``` **HDL Example 4.5 (Dataflow: Four-Bit Comparator)** ``` // Dataflow description of a four-bit comparator //V2001, 2005 syntax module mag_compare (output A_It_B, A_eq_B, A_gt_B, input [3: 0] A, B ); assign A_It_B = (A < B); assign A_gt_B = (A > B); assign A_eq_B = (A = = B); endmodule ``` **HDL Example 4.6 (Dataflow: Two-to-One Multiplexer)** ``` // Dataflow description of two-to-one-line multiplexer module mux_2x1_df(m_out, A, B, select); output m_out; input A, B; input select; assign m_out = (select)? A: B; endmodule ``` ## Full Adder and Subtractor **6. Design a Full Adder and Subtractor Circuit.** **Full Adder** - A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. - Two of the input variables, denoted by x and y, represent the two significant bits to be added. The third input, z, represents the carry from the previous lower significant position. The two outputs are designated by the symbols S for sum and C for carry. - **K-Maps for full adder:** - A diagram shows the k-maps for the sum and carry outputs of a full adder. - **Implementation of full adder in sum-of-products form:** - A diagram shows a full adder implemented using logic gates. **Subtractor (Circuit not provided in the image)** ## Octal-to-Binary Encoder **7. Design an Octal-to-Binary Encoder.** - It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. It is assumed that only one input has a value of 1 at any given time. - The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. - Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. - Output y is 1 for octal digits 2, 3, 6, or 7, and - output x is 1 for digits 4, 5, 6, or 7. **Table 4.7 Truth Table of an Octal-to-Binary Encoder** - A table shows the truth table of an octal-to-binary encoder. ## BCD-to-Excess-3 Code Converter **8. Explain the working of Four-bit adders using 4-Full Adders. Design a BCD-to-excess-3 code converter.** - A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. - Since each code uses four bits to represent a decimal digit, there must be four input variables and four output variables. We designate the four input binary variables by the symbols A, B, C, and D, and the four output variables by w, x, y, and z. - ADD 3 to BCD to get Excess -3 Code **Table 4.2 Truth Table for Code Conversion Example** - A table shows the truth table of a BCD-to-excess-3 code converter. - **Logic diagram for BCD-to-excess-3 code converter:** - A diagram shows the logic diagram of a BCD-to-excess-3 code converter implemented using logic gates. ## SR Latch and Edge-Triggered D Flip-Flop **10. Demonstrate the working of SR Latch and Edge-Triggered D Flip-Flop.** (No information about the SR Latch and Edge-Triggered D Flip-Flop is provided in the image.)