Introduction to MOSFETs (EST 160) PDF

Introduction to MOSFETs Introduction to Analog Circuits Design (EST 160) Prepared by: Engr. Rochelle M. Sabarillo What is Doping? Doping is the process of intentionally adding impurities to a semiconductor in order to change its electrical properties....

Introduction to MOSFETs Introduction to Analog Circuits Design (EST 160) Prepared by: Engr. Rochelle M. Sabarillo What is Doping? Doping is the process of intentionally adding impurities to a semiconductor in order to change its electrical properties. Department of Electronics Engineering 2 What is Doping? In short, doping is used to increase electron or hole concentration. A dopant, also called a doping agent, is any impurity deliberately added to a semiconductor for the purpose of modifying its electrical conductivity. Related illustration: https://www.youtube.com/watch?v=Q5FnIv-pDEQ Department of Electronics Engineering 3 Mobility In solid-state physics, the electron mobility characterises how quickly an electron can move through a metal or semiconductor, when pulled by an electric field. There is an analogous quantity for holes, called hole mobility. The term carrier mobility refers in general to both electron and hole mobility. The only difference between electrons and holes is in their energy and, therefore, in velocity. The effective mass is a result of electron interaction with lattice, i.e. with phonons. As the hole velocity is smaller, a hole spends more time in the interaction region, i.e. holes strongly interact with phonons. The mobility is inversely proportional to the effective mass and the effective mass of hole is much higher than that of electron. Thus the electron mobility is higher than that of hole. Department of Electronics Engineering 4 Department of Electronics Engineering 5 Depletion MOSFET vs. Enhancement MOSFET Department of Electronics Engineering 6 MOSFET Symbols The circuit symbols used to represent NMOS and PMOS transistors are shown below: Department of Electronics Engineering 7 MOSFET as a Switch Shown below is the symbol for an n-type MOSFET, revealing three terminals: gate (G), source (S), and drain (D). The latter two are interchangeable because the device is symmetric. When operating as a switch, the transistor “connects” the source and the drain together if the gate voltage, VG, is “high” and isolates the source and the drain if V G is “low. Department of Electronics Engineering 8 MOSFET Structure Figure below shows a simplified structure of an n-type MOS (NMOS) device. Fabricated on a p-type substrate (also called the “bulk” or the “body”), the device consists of two heavily-doped n regions forming the source and drain terminals, a heavily-doped (conductive) piece of polysilicon (simply called “poly”) operating as the gate, and a thin layer of silicon dioxide (SiO2) (simply called “oxide”) insulating the gate from the substrate. The useful action of the device occurs in the substrate region under the gate oxide. Note that the structure is symmetric with respect to S and D. The lateral dimension of the gate along the source-drain path is called the length, L, and that perpendicular to the length is called the width, W. Department of Electronics Engineering 9 MOSFET Structure In reality, the substrate potential greatly influences the device characteristics. That is, the MOSFET is a four-terminal device. Since in typical MOS operation, the S/D junction diodes must be reverse-biased, we assume that the substrate of NMOS transistors is connected to the most negative supply in the system. For example, if a circuit operates between zero and 1.2 volts, V sub,NMOS = 0. The actual connection is usually provided through an ohmic p+ region, as depicted in the side view of the device below: Department of Electronics Engineering 10 MOSFET Structure In complementary MOS (CMOS) technologies, both NMOS and PMOS transistors are available. From a simplistic viewpoint, the PMOS device is obtained by negating all of the doping types (including the substrate) [(a)], but in practice, NMOS and PMOS devices must be fabricated on the same wafer, i.e., the same substrate. For this reason, one device type can be placed in a “local substrate,” usually called a “well.” In today’s CMOS processes, the PMOS device is fabricated in an n-well [(b)]. Note that the n-well must be connected to a potential such that the S/D junction diodes of the PMOS transistor remain reverse- biased under all conditions. In most circuits, the n-well is tied to the most positive supply voltage. Department of Electronics Engineering 11 MOSFET Structure Figure (b) indicates an interesting difference between NMOS and PMOS transistors: while all NFETs share the same substrate, each PFET can have an independent n-well. This flexibility of PFETs is exploited in some analog circuits. Department of Electronics Engineering 1 2 Threshold Voltage: VTH NMOS What happens as the gate voltage, VG, increases from zero? Since the gate, the dielectric, and the substrate form a capacitor, as VG becomes more positive, the holes in the p-substrate are repelled from the gate area, leaving negative ions behind so as to mirror the charge on the gate. In other words, a depletion region is created (Figure b). Under this condition, no current flows because no charge carriers are available. As VG increases, so do the width of the depletion region and the potential at the oxide-silicon interface. In a sense, the structure resembles a voltage divider consisting of two capacitors in series: the gate-oxide capacitor and the depletion-region capacitor (Figure c). When the interface potential reaches a sufficiently positive value, electrons flow from the source to the interface and eventually to the drain. Thus, a “channel” of charge carriers is formed under the gate oxide between S and D, and the transistor is “turned on.” We say the interface is “inverted.” For this reason, the channel is also called the “inversion layer.” The value of VG for which this occurs is called the “threshold voltage,” VTH. If VG rises further, the charge in the depletion region remains relatively constant while the channel charge density continues to increase, providing a greater current from S to D. The NMOS device turns on abruptly for VGS ≥ VTH. Department of Electronics Engineering 1 3 MOS I/V Characteristics Department of Electronics Engineering 1 4 Threshold Voltage: VTH PMOS The turn-on phenomenon in a PMOS device is similar to that of NFETs, but with all the polarities reversed. As shown in the figure below, if the gate-source voltage becomes sufficiently negative, an inversion layer consisting of holes is formed at the oxide-silicon interface, providing a conduction path between the source and the drain. That is, the threshold voltage of a PMOS device is typically negative. The PMOS device turns on abruptly for VSG ≥ |VTH|. Department of Electronics Engineering 1 5 vs Department of Electronics Engineering 1 6 MOSFET Operating Regions 1.Cut-off 2.Linear/Triode/Ohmic 3.Saturation Department of Electronics Engineering 1 7 Triode Region Since ID is constant along the channel, Note that L is the effective channel length. Figure here plots the parabolas given by the equation above for different values of VGS, indicating that the “current capability” of the device increases with VGS. The peak of each parabola occurs at VDS = VGS − VTH and the peak current is VGS − VTH the “overdrive voltage” and W/L the “aspect ratio.” If VDS ≤ VGS − VTH, we say the device operates in the “triode region.” Department of Electronics Engineering 1 8 Deep Triode Region If VDS