4 + 5.pdf

Objectives Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple architecture invented to illuminate these basic concepts, and how it relates to some real architectures. Know how the program assembly p...

Objectives Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple architecture invented to illuminate these basic concepts, and how it relates to some real architectures. Know how the program assembly process works. 1 Weekly Learning Outcomes 1. CPU basics and organization 2. Memory organization and addressing 3. Instruction processing 2 CPU Basics (1 of 2) The computer’s CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit. – The datapath consists of an arithmetic-logic unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory. – Various CPU components perform sequenced operations according to signals provided by its control unit. 3 CPU Basics (2 of 2) Registers hold data that can be readily accessed by the CPU. They can be implemented using D flip-flops. – A 32-bit register requires 32 D flip-flops. The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit. The control unit determines which actions to carry out according to the values in a program counter register and a status register. 4 The Bus (1 of 5) The CPU shares data with other system components by way of a data bus. – A bus is a set of wires that simultaneously convey a single bit along each line. Two types of buses are commonly found in computer systems: point-to-point, and multipoint buses. These are point-to-point buses: 5 The Bus (2 of 5) Buses consist of data lines, control lines, and address lines. While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the bus. Address lines determine the location of the source or destination of the data. The next slide shows a model bus configuration. 6 The Bus (3 of 5) 7 The Bus (4 of 5) A multipoint bus is shown below. Because a multipoint bus is a shared resource, access to it is controlled through protocols, which are built into the hardware. 8 The Bus (5 of 5) In a master-slave configuration, where more than one device can be the bus master, concurrent bus master requests must be arbitrated. Four categories of bus arbitration are: – Daisy chain: Permissions are passed from the highest-priority device to the lowest. – Centralized parallel: Each device is directly connected to an arbitration circuit. – Distributed using self-detection: Devices decide which gets the bus among themselves. – Distributed using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again. 9 Clocks (1 of 2) Every computer contains at least one clock that synchronizes the activities of its components. A fixed number of clock cycles are required to carry out each data movement or computational operation. The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. Clock cycle time is the reciprocal of clock frequency. – An 800 MHz clock has a cycle time of 1.25 ns. 10 Clocks (2 of 2) Clock speed should not be confused with CPU performance. The CPU time required to run a program is given by the general performance equation: – We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock cycle. We will return to this important equation in later chapters. 11 The Input/Output Subsystem A computer communicates with the outside world through its input/output (I/O) subsystem. I/O devices connect to the CPU through various interfaces. I/O can be memory-mapped—where the I/O device behaves like main memory from the CPU’s point of view. Or I/O can be instruction-based, where the CPU has a specialized I/O instruction set. We study I/O in detail in chapter 7. 12 Memory Organization (1 of 8) Computer memory consists of a linear array of addressable storage cells that are similar to registers. Memory can be byte-addressable, or wordaddressable, where a word typically consists of two or more bytes. Memory is constructed of RAM chips, often referred to in terms of length  width. If the memory word size of the machine is 16 bits, then a 4M  16 RAM chip gives us 4 mega 16-bit memory locations. 13 Memory Organization (2 of 8) How does the computer access a memory location corresponds to a particular address? We observe that 4M can be expressed as 22  220 = 222 words. The memory locations for this memory are numbered 0 through 222 – 1. Thus, the memory bus of this system requires at least 22 address lines. – The address lines “count” from 0 to 222 – 1 in binary. Each line is either “on” or “off” indicating the location of the desired memory element. 14 Memory Organization (3 of 8) Physical memory usually consists of more than one RAM chip. Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips With low-order interleaving, the low order bits of the address specify which memory bank contains the address of interest. Accordingly, in high-order interleaving, the high order address bits specify the memory bank. The next two slides illustrate these two ideas. 15 Memory Organization (4 of 8) Example: Suppose we have a memory consisting of 16 2K x 8 bit chips. – Memory is 32K = 25  210 = 215 – 15 bits are needed for each address. – We need 4 bits to select the chip, and 11 bits for the offset into the chip that selects the byte. 16 Memory Organization (5 of 8) In high-order interleaving the high-order 4 bits select the chip. In low-order interleaving the low-order 4 bits select the chip. 17 Memory Organization (6 of 8) 18 Memory Organization (7 of 8) 19 Memory Organization (8 of 8) EXAMPLE 4.1: Suppose we have a 128-word memory that is 8-way low-order interleaved – which means it uses 8 memory banks; 8 = 23 So we use the low-order 3 bits to identify the bank. Because we have 128 words, we need 7 bits for each address (128 = 27). 20 Interrupts The normal execution of a program is altered when an event of higher-priority occurs. The CPU is alerted to such an event through an interrupt. Interrupts can be triggered by I/O requests, arithmetic errors (such as division by zero), or when an invalid instruction is encountered. Each interrupt is associated with a procedure that directs the actions of the CPU when an interrupt occurs. – Nonmaskable interrupts are high-priority interrupts that cannot be ignored. 21 MARIE (1 of 14) We can now bring together many of the ideas that we have discussed to this point using a very simple model computer. Our model computer, the Machine Architecture that is Really Intuitive and Easy (MARIE) was designed for the singular purpose of illustrating basic computer system concepts. While this system is too simple to do anything useful in the real world, a deep understanding of its functions will enable you to comprehend system architectures that are much more complex. 22 MARIE (2 of 14) The MARIE architecture has the following characteristics: – Binary, two's complement data representation. – Stored program, fixed word length data and instructions. – 4K words of word-addressable main memory. – 16-bit data words. – 16-bit instructions, 4 for the opcode and 12 for the address. – A 16-bit arithmetic logic unit (ALU). – Seven registers for control and data movement. 23 MARIE (3 of 14) MARIE’s seven registers are: – (1) Accumulator, AC, a 16-bit register that holds a conditional operator (e.g., "less than") or one operand of a two-operand instruction. – (2) Memory address register, MAR, a 12-bit register that holds the memory address of an instruction or the operand of an instruction. – (3) Memory buffer register, MBR, a 16-bit register that holds the data after its retrieval from, or before its placement in memory. 24 MARIE (4 of 14) – (4) Program counter, PC, a 12-bit register that holds the address of the next program instruction to be executed. – (5) Instruction register, IR, which holds an instruction immediately preceding its execution. – (6) Input register, InREG, an 8-bit register that holds data read from an input device. – (7) Output register, OutREG, an 8-bit register, that holds data that is ready for the output device. 25 MARIE (5 of 14) This is the MARIE architecture shown graphically. 26 MARIE (6 of 14) The registers are interconnected, and connected with main memory through a common data bus. Each device on the bus is identified by a unique number that is set on the control lines whenever that device is required to carry out an operation. Separate connections are also provided between the accumulator and the memory buffer register, and the ALU and the accumulator and memory buffer register. This permits data transfer between these devices without use of the main data bus. 27 MARIE (7 of 14) This is the MARIE data path shown graphically. 28 MARIE (8 of 14) A computer’s instruction set architecture (ISA) specifies the format of its instructions and the primitive operations that the machine can perform. The ISA is an interface between a computer’s hardware and its software. Some ISAs include hundreds of different instructions for processing data and controlling program execution. The MARIE ISA consists of only 13 instructions. 29 MARIE (9 of 14) This is the format of a MARIE instruction: The fundamental MARIE instructions are: 30 MARIE (10 of 14) This is a bit pattern for a LOAD instruction as it would appear in the IR: We see that the opcode is 1 and the address from which to load the data is 3. 31 MARIE (11 of 14) This is a bit pattern for a SKIPCOND instruction as it would appear in the IR: We see that the opcode is 8 and bits 11 and 10 are 10, meaning that the next instruction will be skipped if the value in the AC is greater than zero. What is the hexadecimal representation of this instruction? 32 MARIE (12 of 14) Each of our instructions actually consists of a sequence of smaller instructions called microoperations. The exact sequence of microoperations that are carried out by an instruction can be specified using register transfer language (RTL). In the MARIE RTL, we use the notation M[X] to indicate the actual data value stored in memory location X, and  to indicate the transfer of bytes to a register or memory location. 33 MARIE (13 of 14) The RTL for the LOAD instruction is: MAR  X MBR  M[MAR] AC  MBR Similarly, the RTL for the ADD instruction is: MAR  X MBR  M[MAR] AC  AC + MBR 34 MARIE (14 of 14) Recall that SKIPCOND skips the next instruction according to the value of the AC. The RTL for this instruction is the most complex in our instruction set: If IR[11 - 10] = 00 then If AC < 0 then PC  PC + 1 else If IR[11 - 10] = 01 then If AC = 0 then PC  PC + 1 else If IR[11 - 10] = 10 then If AC > 0 then PC  PC + 1 35 Instruction Processing (1 of 7) The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program. We first have to fetch an instruction from memory, and place it into the IR. Once in the IR, it is decoded to determine what needs to be done next. If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. With everything in place, the instruction is executed. The next slide shows a flowchart of this process. 36 Instruction Processing (2 of 7) 37 Instruction Processing (3 of 7) All computers provide a way of interrupting the fetch-decode-execute cycle. Interrupts are asynchronous and indicate some type of service is required. Interrupts occur when: – A user break (e.g., Control+C) is issued – I/O is requested by the user or a program – A critical error occurs Interrupts can be caused by hardware or software. – Software interrupts are also called traps. 38 Instruction Processing (4 of 7) Interrupt processing involves adding another step to the fetch-decode-execute cycle as shown below. The next slide shows a flowchart of “Process the interrupt.” 39 Instruction Processing (5 of 7) 40 Instruction Processing (6 of 7) For general-purpose systems, it is common to disable all interrupts during the time in which an interrupt is being processed. – Typically, this is achieved by setting a bit in the flags register. Interrupts that are ignored in this case are called maskable. Nonmaskable interrupts are those interrupts that must be processed in order to keep the system in a stable condition. 41 Instruction Processing (7 of 7) Interrupts are very useful in processing I/O. However, interrupt-driven I/O is complicated, and is beyond the scope of our present discussion. – We will look into this idea in greater detail in Chapter 7. MARIE, being the simplest of simple systems, uses a modified form of programmed I/O. All output is placed in an output register (OutREG) and the CPU polls the input register (InREG) until input is sensed, at which time the value is copied into the accumulator. 42 A Simple Program (1 of 3) Consider the simple MARIE program given below. We show a set of mnemonic instructions stored at addresses 0x100 – 0x106 (hex): 43 A Simple Program (2 of 3) Let’s look at what happens inside the computer when our program runs. This is the LOAD 104 instruction: 44 A Simple Program (3 of 3) Our second instruction is ADD 105: 45 A Discussion on Assemblers (1 of 4) Mnemonic instructions, such as LOAD 104, are easy for humans to write and understand. They are impossible for computers to understand. Assemblers translate instructions that are comprehensible to humans into the machine language that is comprehensible to computers – We note the distinction between an assembler and a compiler: In assembly language, there is a one-to-one correspondence between a mnemonic instruction and its machine code. With compilers, this is not usually the case. 46 A Discussion on Assemblers (2 of 4) Assemblers create an object program file from mnemonic source code in two passes. During the first pass, the assembler assembles as much of the program as it can, while it builds a symbol table that contains memory references for all symbols in the program. During the second pass, the instructions are completed using the values from the symbol table. 47 A Discussion on Assemblers (3 of 4) Consider our example program at the right. – Note that we have included two directives HEX and DEC that specify the radix of the constants. The first pass, creates a symbol table and the partiallyassembled instructions as shown. 48 A Discussion on Assemblers (4 of 4) After the second pass, the assembly is complete. 49 Extending Our Instruction Set (1 of 6) So far, all of the MARIE instructions that we have discussed use a direct addressing mode. This means that the address of the operand is explicitly stated in the instruction. It is often useful to employ a indirect addressing, where the address of the address of the operand is given in the instruction. – If you have ever used pointers in a program, you are already familiar with indirect addressing. 50 Extending Our Instruction Set (2 of 6) We have included three indirect addressing mode instructions in the MARIE instruction set. The first two are LOADI X and STOREI X where specifies the address of the operand to be loaded or stored. In RTL : LOADI X STOREI X 51 Extending Our Instruction Set (3 of 6) The ADDI X where specifies the address of the operand to be added. In RTL: ADDI X 52 Extending Our Instruction Set (4 of 6) Another helpful programming tool is the use of subroutines. The jump-and-store instruction, JNS, gives us limited subroutine functionality. The details of the JNS instruction are given by the following RTL: PC ← AC Does JNS permit recursive calls? 53 Extending Our Instruction Set (5 of 6) Our first new instruction is the CLEAR instruction. All it does is set the contents of the accumulator to all zeroes. This is the RTL for CLEAR: AC  0 We put our new instructions to work in the program on the following slide. 54 Extending Our Instruction Set (6 of 6) Example 4.2 on the textbook and Ex4_1.mas in the MARIE simulator package: Using loop to add five numbers. 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D | | | | | |Loop | | | | | | | | LOAD Addr STORE Next LOAD Num SUBT One STORE Ctr LOAD Sum ADDI Next STORE Sum LOAD Next ADD One STORE Next LOAD Ctr SUBT One STORE Ctr 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B | | | |Addr |Next |Num |Sum |Ctr |One | | | | | SKIPCOND 000 JUMP Loop HALT HEX 117 HEX 0 DEC 5 DEC 0 HEX 0 DEC 1 DEC 10 DEC 15 20 DEC 2 DEC 25 DEC 30 55 MARIE Assembly Program: Example 4.3 Ex4_2.mas in the MARIE simulator package If, Then, Else, Endif, X, Y, ORG 100 Load X Subt Y Skipcond 400 Jump Else Load X Add X Store X Jump Endif Load Y Subt X Store Y Halt Dec 12 Dec 20 END /Load the first value /Subtract the value of Y, store result in AC /If AC=0, skip the next instruction /Jump to Else part if AC is not equal to 0 /Reload X so it can be doubled /Double X /Store the new value /Skip over the false, or else, part to end of if /Start the else part by loading Y /Subtract X from Y /Store Y-X in Y /Terminate program (it doesn't do much!) /Load the loop control variable /Subtract one from the loop control variable If X = Y then X=X×2 else Y=Y- X 56 MARIE Assembly Program: Example 4.4 Ex4_3.mas in the MARIE simulator package / This program traverses a string and outputs each / character. The string is terminated with a null. / Note: By changing the output window control setting / to "no linefeeds" the text will print in a single / line, rather than in a column of single characters. Getch, ORG 100 LoadI Chptr Skipcond 400 Jump Outp Halt / Load the character found at address chptr. / If the character is a null, we are done. / Otherwise, proceed with operation. 57 MARIE Assembly Program: Example 4.4 Outp, One, Chptr, String, Output Load Add Store Jump Hex Hex Dec Dec Dec Dec Dec Dec Dec Dec Dec Dec Dec Dec Dec END Chptr One Chptr Getch 0001 10B 072 101 108 108 111 032 119 111 114 108 100 033 000 / Output the character. / Move pointer to next character. /H /e /l /l /o / [space] /w /o /r /l /d /! / [null] 58 MARIE Assembly Program: Example 4.5 Ex4_4.mas in the MARIE simulator package /This example illustrates the use of a simple subroutine to double the value stored at X Loop, X, Y, Temp, ORG Load Store JnS Store Load Store JnS Store Y Halt DEC DEC DEC 100 X Temp Subr X Y Temp Subr / Load the first number to be doubled. / Use Temp as a parameter to pass value to Subr. / Store the return address, and jump to the procedure. / Store the first number, doubled / Load the second number to be doubled. / Store the return address and jump to the procedure. / Store the second number doubled. / End program. 20 48 0 59 MARIE Assembly Program: Example 4.5 Subr, HEX Load Add JumpI END 0 Temp Temp Subr / Store return address here. / Actual subroutine to double numbers. / AC now holds double the value of Temp. / Return to calling code. 60 A Discussion on Decoding (1 of 11) A computer’s control unit keeps things synchronized, making sure that bits flow to the correct components as the components are needed. There are two general ways in which a control unit can be implemented: hardwired control and microprogrammed control. – With microprogrammed control, a small program is placed into read-only memory in the microcontroller. – Hardwired controllers implement this program using digital logic components. 61 A Discussion on Decoding (2 of 11) Your text provides a complete list of the register transfer language for each of MARIE’s instructions. The microoperations given by each RTL define the operation of MARIE’s control unit. Each microoperation consists of a distinctive signal pattern that is interpreted by the control unit and results in the execution of an instruction. – Recall, the RTL for the Add instruction is: MAR  X MBR  M[MAR] AC  AC + MBR 62 A Discussion on Decoding (3 of 11) Each of MARIE’s registers and main memory have a unique address along the datapath. The addresses take the form of signals issued by the control unit. How many signal lines does MARIE’s control unit need? 63 A Discussion on Decoding (4 of 11) Let us define two sets of three signals. One set, P2, P1, P0, controls reading from memory or a register, and the other set consisting of P5, P4, P3, controls writing to memory or a register. The next slide shows a close up view of MARIE’s MBR. 64 A Discussion on Decoding (5 of 11) The register MBR is enabled for reading when P0 and P1 are high, and enabled for writing when P3 and P4 are high. 65 A Discussion on Decoding (6 of 11) Careful inspection of MARIE’s RTL reveals that the ALU has only three operations: add, subtract, and clear. – We will also define a fourth “do nothing” state. The entire set of MARIE’s control signals consists of: – Register controls: P0 through P5, MR , and MW. – ALU controls: A0 through A1 and LALT to control the ALU’s data source. – Timing: T0 through T7 and counter reset Cr 66 A Discussion on Decoding (7 of 11) Consider MARIE’s Add instruction. Its RTL is: MAR  X MBR  M[MAR] AC  AC + MBR After an Add instruction is fetched, the address, X, is in the rightmost 12 bits of the IR, which has a datapath address of 7. X is copied to the MAR, which has a datapath address of 1. Thus we need to raise signals P0, P1, and P2 to read from the IR, and signal P3 to write to the MAR. 67 A Discussion on Decoding (8 of 11) Here is the complete signal sequence for MARIE’s Add instruction: P3 P2 P1 P0 T3 : MAR  X P4 P3 T4 MR : MBR  M[MAR] Cr A0 P5 T5 LALT : AC  AC + MBR [Reset counter] These signals are ANDed with combinational logic to bring about the desired machine behavior. The next slide shows the timing diagram for this instruction. 68 A Discussion on Decoding (9 of 11) Notice the concurrent signal states during each machine cycle: C3 through C5. P3 P2 P1 P0 T3 : MAR  X P4 P3 T 4 M R : MBR  M[MAR] Cr A0 P5 T5 LALT : AC  AC + MBR [Reset counter] 69 A Discussion on Decoding (10 of 11) We note that the signal pattern just described is the same whether our machine used hardwired or microprogrammed control. In hardwired control, the bit pattern of machine instruction in the IR is decoded by combinational logic. The decoder output works with the control signals of the current system state to produce a new set of control signals. A block diagram of a hardwired control unit is shown on the following slide. 70 A Discussion on Decoding (11 of 11) 71 Conclusion (1 of 2) The major components of a computer system are its control unit, registers, memory, ALU, and data path. A built-in clock keeps everything synchronized. Control units can be microprogrammed or hardwired. Hardwired control units give better performance, while microprogrammed units are more adaptable to changes. 72 Conclusion (2 of 2) Computers run programs through iterative fetch-decode-execute cycles. Computers can run programs that are in machine language. An assembler converts mnemonic code to machine language. The Intel architecture is an example of a CISC architecture; MIPS is an example of a RISC architecture. 73 Objectives Understand the factors involved in instruction set architecture design. Gain familiarity with memory addressing modes. Understand the concepts of instructionlevel pipelining and its affect upon execution performance. 74 Weekly Learning Outcomes 1. INSTRUCTION FORMATS 2. INSTRUCTION TYPES 3. ADRESSING 75 Introduction This chapter builds upon the ideas in Chapter 4. We present a detailed look at different instruction formats, operand types, and memory access methods. We will see the interrelation between machine organization and instruction formats. This leads to a deeper understanding of computer architecture in general. 76 Instruction Formats (1 of 31) Instruction sets are differentiated by the following: – – – – – – Number of bits per instruction. Stack-based or register-based. Number of explicit operands per instruction. Operand location. Types of operations. Type and size of operands. 77 Instruction Formats (2 of 31) Instruction set architectures are measured according to: – – – – Main memory space occupied by a program. Instruction complexity. Instruction length (in bits). Total number of instructions in the instruction set. 78 Instruction Formats (3 of 31) In designing an instruction set, consideration is given to: – Instruction length. Whether short, long, or variable. – Number of operands. – Number of addressable registers. – Memory organization. Whether byte- or word addressable. – Addressing modes. Choose any or all: direct, indirect or indexed. 79 Instruction Formats (4 of 31) Byte ordering, or endianness, is another major architectural consideration. If we have a two-byte integer, the integer may be stored so that the least significant byte is followed by the most significant byte or vice versa. – In little endian machines, the least significant byte is followed by the most significant byte. – Big endian machines store the most significant byte first (at the lower address). 80 Instruction Formats (5 of 31) As an example, suppose we have the hexadecimal number 0x12345678. The big endian and small endian arrangements of the bytes are shown below. 81 Instruction Formats (6 of 31) A larger example: A computer uses 32bit integers. The values 0xABCD1234, 0x00FE4321, and 0x10 would be stored sequentially in memory, starting at address 0x200 as here. 82 Instruction Formats (7 of 31) Big endian: – Is more natural. – The sign of the number can be determined by looking at the byte at address offset 0. – Strings and integers are stored in the same order. Little endian: – Makes it easier to place values on non-word boundaries. – Conversion from a 16-bit integer address to a 32-bit integer address does not require any arithmetic. 83 Instruction Formats (8 of 31) The next consideration for architecture design concerns how the CPU will store data. We have three choices: – 1. A stack architecture – 2. An accumulator architecture – 3. A general purpose register architecture In choosing one over the other, the tradeoffs are simplicity (and cost) of hardware design with execution speed and ease of use. 84 Instruction Formats (9 of 31) In a stack architecture, instructions and operands are implicitly taken from the stack. – A stack cannot be accessed randomly. In an accumulator architecture, one operand of a binary operation is implicitly in the accumulator. – One operand is in memory, creating lots of bus traffic. In a general purpose register (GPR) architecture, registers can be used instead of memory. – Faster than accumulator architecture. – Efficient implementation for compilers. – Results in longer instructions. 85 Instruction Formats (10 of 31) Most systems today are GPR systems. There are three types: – Memory-memory where two or three operands may be in memory. – Register-memory where at least one operand must be in a register. – Load-store where no operands may be in memory. The number of operands and the number of available registers has a direct affect on instruction length. 86 Instruction Formats (11 of 31) Stack machines use one - and zero-operand instructions. LOAD and STORE instructions require a single memory address operand. Other instructions use operands from the stack implicitly. PUSH and POP operations involve only the stack’s top element. Binary instructions (e.g., ADD, MULT) use the top two items on the stack. 87 Instruction Formats (12 of 31) Stack architectures require us to think about arithmetic expressions a little differently. We are accustomed to writing expressions using infix notation, such as: Z = X + Y. Stack arithmetic requires that we use postfix notation: Z = XY+. – This is also called reverse Polish notation, (somewhat) in honor of its Polish inventor, Jan Lukasiewicz (1878–1956). 88 Instruction Formats (13 of 31) The principal advantage of postfix notation is that parentheses are not used. For example, the infix expression, Z = (X + Y)  (W + U) becomes: Z = X Y + W U +  in postfix notation. 89 Instruction Formats (14 of 31) Example: Convert the infix expression (2+3) – 6/3 to postfix: 90 Instruction Formats (15 of 31) Example: Convert the infix expression (2+3) – 6/3 to postfix: 91 Instruction Formats (16 of 31) Example: Convert the infix expression (2+3) – 6/3 to postfix: 92 Instruction Formats (17 of 31) Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - : 93 Instruction Formats (18 of 31) Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - : 94 Instruction Formats (19 of 31) Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - : 95 Instruction Formats (20 of 31) Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - : 96 Instruction Formats (21 of 31) Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - : 97 Instruction Formats (22 of 31) Let's see how to evaluate an infix expression using different instruction formats. With a three-address ISA, (e.g., mainframes), the infix expression, Z = X  Y + W  U might look like this: MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 98 Instruction Formats (23 of 31) In a two-address ISA, (e.g., Intel, Motorola), the infix expression, Z = X  Y + W  U might look like this: LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U Note: One-address ADD R1,R2 ISAs usually require one operand to be a STORE Z,R1 register. 99 Instruction Formats (24 of 31) In a one-address ISA, like MARIE, the infix expression, Z = X  Y + W  U looks like this: LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z 100 Instruction Formats (25 of 31) In a stack ISA, the postfix expression, Z = X Y  W U  + might look like this: PUSH X PUSH Y Would this program require MULT more execution time than the PUSH W corresponding (shorter) PUSH U program that we saw in the MULT 3-address ISA? ADD POP Z 101 Instruction Formats (26 of 31) We have seen how instruction length is affected by the number of operands supported by the ISA. In any instruction set, not all instructions require the same number of operands. Operations that require no operands, such as HALT, necessarily waste some space when fixed-length instructions are used. One way to recover some of this space is to use expanding opcodes. 102 Instruction Formats (27 of 31) A system has 16 registers and 4K of memory. We need 4 bits to access one of the registers. We also need 12 bits for a memory address. If the system is to have 16-bit instructions, we have two choices for our instructions: 103 Instruction Formats (28 of 31) If we allow the length of the opcode to vary, we could create a very rich instruction set: 104 Instruction Formats (29 of 31) Example: Given 8-bit instructions, is it possible to allow the following to be encoded? – 3 instructions with two 3-bit operands – 2 instructions with one 4-bit operand – 4 instructions with one 3-bit operand We need: – 3  23  23 = 192 bits for the 3-bit operands – 2  24 = 32 bits for the 4-bit operands – 4  23 = 32 bits for the 3-bit operands Total: 256 bits. 105 Instruction Formats (30 of 31) With a total of 256 bits required, we can exactly encode our instruction set in 8 bits! We need: – 3  23  23 = 192 bits for the 3-bit operands – 2  24 = 32 bits for the 4-bit operands – 4  23 = 32 bits for the 3-bit operands Total: 256 bits. One such encoding is shown on the next slide. 106 Instruction Formats (31 of 31) 107 Instruction Types Instructions fall into several broad categories that you should be familiar with: – – – – Data movement. Arithmetic. Boolean. Bit manipulation. – I/O. – Control transfer. – Special purpose. Can you think of some examples of each of these? 108 Addressing (1 of 6) Addressing modes specify where an operand is located. They can specify a constant, a register, or a memory location. The actual location of an operand is its effective address. Certain addressing modes allow us to determine the address of an operand dynamically. 109 Addressing (2 of 6) Immediate addressing is where the data is part of the instruction. Direct addressing is where the address of the data is given in the instruction. Register addressing is where the data is located in a register. Indirect addressing gives the address of the address of the data in the instruction. Register indirect addressing uses a register to store the address of the address of the data. 110 Addressing (3 of 6) Indexed addressing uses a register (implicitly or explicitly) as an offset, which is added to the address in the operand to determine the effective address of the data. Based addressing is similar except that a base register is used instead of an index register. The difference between these two is that an index register holds an offset relative to the address given in the instruction, a base register holds a base address where the address field represents a displacement from this base. 111 Addressing (4 of 6) In stack addressing the operand is assumed to be on top of the stack. There are many variations to these addressing modes including: – – – – Indirect indexed. Base/offset. Self-relative. Auto increment—decrement. We won’t cover these in detail. Let’s look at an example of the principal addressing modes. 112 Addressing (5 of 6) For the instruction shown, what value is loaded into the accumulator for each addressing mode? 113 Addressing (6 of 6) For the instruction shown, what value is loaded into the accumulator for each addressing mode? 0x500 114 Instruction Pipelining (1 of 3) Some CPUs divide the fetch-decodeexecute cycle into smaller steps. These smaller steps can often be executed in parallel to increase throughput. Such parallel execution is called instruction pipelining. Instruction pipelining provides for instruction level parallelism (ILP) The next slide shows an example of instruction pipelining. 115 Instruction Pipelining (2 of 3) Suppose a fetch-decode-execute cycle were broken into the following smaller steps: 1. 2. 3. 4. 5. 6. Fetch instruction Decode opcode Calculate effective address of operands Fetch operands Execute instruction Store result Suppose we have a six-stage pipeline. S1 fetches the instruction, S2 decodes it, S3 determines the address of the operands, S4 fetches them, S5 executes the instruction, and S6 stores the result. 116 Instruction Pipelining (3 of 3) For every clock cycle, one small step is carried out, and the stages are overlapped. S1. Fetch instruction. S2. Decode opcode. S3. Calculate effective address of operands. S4. Fetch operands. S5. Execute. S6. Store result. 117 Conclusion (1 of 2) ISAs are distinguished according to their bits per instruction, number of operands per instruction, operand location and types and sizes of operands. Endianness as another major architectural consideration. CPU can store data based on: – A stack architecture – An accumulator architecture – A general purpose register architecture. 118 Conclusion (2 of 2) Instructions can be fixed length or variable length. To enrich the instruction set for a fixed length instruction set, expanding opcodes can be used. The addressing mode of an ISA is also another important factor. We looked at: – – – – Immediate Register Indirect Based – Direct – Register Indirect – Indexed – Stack 119