CE 302 Week 8 Revision PDF

CE 302 Week 8 Revision Register addressing modes u MOV AL,BL 8 bits Copies BL into AL u MOV CH,CL 8 bits Copies CL into CH u MOV AX,CX 16 bits Copies CX into AX u MOV SP,BP 16 bits Copies BP into SP u MOV DS,AX 16 bits Copies AX into DS u MOV SI,DI 16 bits Copies DI into SI...

CE 302 Week 8 Revision Register addressing modes u MOV AL,BL 8 bits Copies BL into AL u MOV CH,CL 8 bits Copies CL into CH u MOV AX,CX 16 bits Copies CX into AX u MOV SP,BP 16 bits Copies BP into SP u MOV DS,AX 16 bits Copies AX into DS u MOV SI,DI 16 bits Copies DI into SI u MOV BX,ES 16 bits Copies ES into BX u MOV DS,CX 16 bits Copies CX into DS u MOV ES,DS — Not allowed (segment-to-segment) u MOV BL,DX — Not allowed (mixed sizes) u MOV CS,AX — Not allowed (the code segment register may not be the destination register) İmmediate addressing u MOV BL,44 8 bits Copies 44 decimal (2CH) into BL u MOV AX,44H 16 bits Copies 0044H into AX u MOV SI,0 16 bits Copies 0000H into SI u MOV CH,100 8 bits Copies 100 decimal (64H) into CH u MOV AL,’A’ 8 bits Copies ASCII A into AL u MOV AX,’AB’ 16 bits Copies ASCII BA* into AX u MOV CL,11001110B 8 bits Copies 11001110 binary into CL Direct addressing Instruction Explanation MOV AX,COW 16 bits Copies the word contents of data segment memory location COW into AX MOV NEWS,AL 8 bits Copies AL into byte memory location NEWS MOV ES:[2000H],AL 8 bits Copies AL into extra segment memory at offset address 2000 H MOV AL,MOUSE 8 bits Copies the contents of location MOUSE into AL; MOV THERE,AX Copies AX into word memory location THERE MOV AL,NUMBER 8 bits Copies the byte contents of data segment memory location NUMBER into AL Register indirect addressing. u MOV CX,[BX] 16 bits Copies the word contents of the data segment memory location addressed by BX into CX u MOV [BP],DL 8 bits Copies DL into the stack segment memory location addressed by BP u MOV [DI],BH 8 bits Copies BH into the data segment memory location addressed by DI u MOV [DI],[BX] — Memory-to-memory transfers are not allowed except with string instructions.DATA ;start data segment DATAS DW 50 DUP(?) ;setup array of 50 words 0000.CODE ;start code segment MOV AX,0 MOV ES,AX ;address segment 0000 with ES MOV BX,OFFSET DATAS ;address DATAS array with BX Example MOV CX,50 ;load counter with 50 AGAIN: MOV AX, value ;get any value MOV [BX],AX ;save value in DATAS INC BX ;increment BX to next element INC BX LOOP AGAIN ;repeat 50 times Example MOV BX,OFFSET ARRAY ;address ARRAY MOV DI,10H ;address element 10H MOV AL,[BX+DI] ;get element 10H MOV DI,20H ;address element 20H MOV [BX+DI],AL ;save in element 20H mov ax,"ab” mov bx,23edh mov ,bx INTRODUCTION TO PROGRAM SEGMENTS code segment u Calculate the physical address of an instruction: – The microprocessor will retrieve the instruction from memory locations starting at 2E5F3. INTRODUCTION TO PROGRAM SEGMENTS code segment u Calculate the physical address of an instruction: – Since IP can have a minimum value of 0000H and a maximum of FFFFH, the logical address range in this example is 2500:0000 to 2500:FFFF.  INTRODUCTION TO PROGRAM SEGMENTS code segment u Calculate the physical address of an instruction: – This means that the lowest memory location of the code segment above will be 25000H (25000 + 0000) and the highest memory location will be 34FFFH (25000 + FFFF). INTRODUCTION TO PROGRAM SEGMENTS code segment u What happens if the desired instructions are located beyond these two limits? u The value of CS must be changed to access those instructions.  FLAG REGISTER u Six flags, called conditional flags, indicate some condition resulting after an instruction executes. – These six are CF, PF, AF, ZF, SF, and OF. – The remaining three, often called control flags, control the operation of instructions before they are executed.  FLAG REGISTER flag register and ADD instruction u Flag bits affected by the ADD instruction: u CF (carry flag); PF (parity flag); AF (auxiliary carry flag). u ZF (zero flag); SF (sign flag); OF (overflow flag). Stack example MODEL TINY ;select tiny model.CODE ;start code segment MOV AX,1000H ;load test data MOV BX,2000H MOV CX,3000H PUSH AX ;1000H to stack PUSH BX ;2000H to stack PUSH CX ;3000H to stack POP AX ;3000H to AX POP CX ;2000H to CBX POP BX ;1000H to BX THE STACK pushing onto the stack u As each PUSH is executed, the register contents are saved on the stack and SP is decremented by 2. Load effective address - LEA u The OFFSET directive performs the same function as an LEA instruction if the operand is a displacement. u For example, the MOV BX,OFFSET LIST performs the same function as LEA BX,LIST. u Both instructions load the offset address of memory location LIST into the BX register. u But why is the LEA instruction available if the OFFSET directive accomplishes the same task? u First, OFFSET only functions with simple operands such as LIST. It may not be used for an operand such as [DI], LIST [SI], and so on. u The OFFSET directive is more efficient than the LEA instruction for simple operands. It takes the microprocessor longer to execute the LEA BX,LIST instruction than the MOV BX,OFFSET LIST. Example LEA.DATA ;start data segment DATA1 DW 2000H ;define DATA1 DATA2 DW 3000H ;define DATA2.CODE ;start code segment LEA SI,DATA1 ;address DATA1 with SI MOV DI,OFFSET DATA2 ;address DATA2 with DI MOV BX,[SI] ;exchange DAT1 with DATA2 MOV CX,[DI] MOV [SI],CX MOV [DI],BX END LEA and OFFSET comparison ; lea and offset examples data segment data1 db 2,6,5 lea si,data2 ;si= 04 data2 db 7,8,9 ends mov cl,[si] ; cl= 08 mov di,offset [si] ;di=0 code segment lea di,[si] ; di=04 start: ; set segment registers: mov ax, data mov ch,[di] ;ch=08 mov ds, ax mov es, ax add [di],al ;ds:0004 =5 mov al,5 mov ax, 4c00h ; exit to operating system. int 21h mov bx,offset data1 ; bx=0001 ends mov dl,[bx] ; dl=06 mov di,offset data1 ; di=02 end start ; mov dh,[di] ;dh=05 Offset value mov bx,0 L1: add bx,[di] inc di inc di dec cx jnz L1 mov word ptr[si], sum F9 is 2’s complement of 7, (15H-0EH) 15 is the offset of next instruction after the “jmp” Addition u ADD AL,BL AL = AL + BL u ADD CX,DI CX = CX + DI u ADD CL,44H CL = CL + 44H u ADD BX,245FH BX = BX + 245FH u ADD [BX],AL AL adds to the byte contents of the data segment memory location addressed by BX with the sum already stored in the same memory location u ADD CL,[BP] The byte contents of the stack segment memory location addressed by BP add to CL with the sum stored in CL Example MOV DI,OFFSET NUMB ;address NUMB MOV AL,0 ;clear sum ADD AL,[DI] ;add NUMB ADD AL,[DI+1] ;add NUMB+1 Array addition MOV AL,0 ;clear sum MOV SI,3 ;address element 3 ADD AL,ARRAY[SI] ;add element 3 ADD AL,ARRAY[SI+2] ;add element 5 ADD AL,ARRAY[SI+4] ;add element 7 UNSIGNED ADDITION AND SUBTRACTION CASE1 addition of individual byte/word data u Due to pipelining it is strongly recommended that the following lines of the program be replaced: – The "ADC AH,00" instruction in reality means add 00+AH+CF and place the result in AH. More efficient since the instruction "JNC OVER" has to empty the queue of pipelined instructions and fetch the instructions from the OVER target every time the carry is zero (CF = 0). UNSIGNED ADDITION AND SUBTRACTION CASE2 addition of multiword numbers ADDING WORDS.DATA COUNT EQU05 ;-------loop--------------------------- DATA DW 27345,28521,29533,30105, 52375 BACK: ADD AX, [SI] ORG 0010H ADC BX, 0 ;add carry to BX SUMDW 2DUP(?) INC SI ;-------------initializing------------- INC SI.CODE DEC CX MAIN PROC FAR JNZ BACK MOV AX, @DATA MOV SUM, AX MOV DS, AX MOV SUM+2, BX MOV AH, 4CH MOV CX, COUNT INT 21H MOV SI, OFFSET DATA MAIN ENDP MOV AX, 00 END MAIN MOV BX, AX ; ; Subtraction u SUB CL,BL CL = CL – BL u SUB AX,SP AX = AX – SP u SUB DH,6FH DH = DH – 6FH u SUB AX,0CCCCH A X = AX – 0CCCCH u SUB [DI],CH Subtracts CH from the byte contents of the data segment memory addressed by DI and stores the difference in the same memory location u SUB CH,[BP] Subtracts the byte contents of the stack segment memory location addressed by BP from CH and stores the difference in CH u SUB AH,TEMP Subtracts the byte contents of memory location TEMP from AH and stores the difference in AH u SUB DI,TEMP[SI] Subtracts the word contents of the data segment memory location addressed by TEMP plus SI from DI and stores the difference in DI  Flags after a subtraction MOV CH,22H SUB CH,44H u Both carry flags (C and A) hold borrows after a subtraction instead of carries, as after an addition. u This example subtracted 44H ( 68) from 22H (34 ), resulting in a 0DEH (-34 ). u Because the outcome is a correct 8-bit signed number, there is no overflow in this example. An 8-bit overflow occurs only if the signed result is greater than or less than - 128 UNSIGNED MULTIPLICATION & DIVISION multiplication of unsigned numbers u In multiplying two numbers in the x86 processor, use of registers AX, AL, AH, and DX is necessary. u The function assumes the use of those registers. u Three multiplication cases: u byte times byte; word times word; byte times word. UNSIGNED MULTIPLICATION & DIVISION multiplication of unsigned numbers u byte × byte - one of the operands must be in the AL register and the second can be in a register or in memory. u After the multiplication, the result is in AX. – 25H is multiplied by 65H and the result is saved in word-sized memory named RESULT. Register addressing mode was used. UNSIGNED MULTIPLICATION & DIVISION multiplication of unsigned numbers u word × word - one operand must be in AX & the second operand can be in a register or memory. u After multiplication, AX & DX will contain the result. u Since word-by-word multiplication can produce a 32-bit result, AX will hold the lower word and DX the higher word. UNSIGNED MULTIPLICATION & DIVISION multiplication of unsigned numbers u word × byte - similar to word-by-word multiplication except that AL contains the byte operand and AH must be set to zero.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u Like multiplication, division of two numbers in the x86 uses of registers AX, AL, AH, and DX. u Four division cases: u byte over byte; u word over word. u word over byte; u doubleword over word.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u Individe, in cases where the CPU cannot perform the division, an interrupt is activated. u Referred to as an exception, and the PC will display a Divide Error message. u If the denominator is zero. (dividing any number by 00) u If the quotient is too large for the assigned register.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u byte/byte - the numerator must be in the AL register and AH must be set to zero. u The denominator cannot be immediate but can be in a register or memory, supported by the addressing modes. u After the DIV instruction is performed, the quotient is in AL and the remainder is in AH.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u Various addressing modes of the denominator.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers DATA7 DB 95 DATA8 DB 10 u Various addressing modes of the denominator. QUOT1 DB ? REMAIN DB ?  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u word/word - the numerator is in AX, and DX must be cleared. u The denominator can be in a register or memory. u After DIV, AX will have the quotient. u The remainder will be in DX.  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u word/byte - the numerator is in AX & the denominator can be in a register or memory. u After DIV, AL will contain the quotient, AH the remainder. u The maximum quotient is FFH. u This program divides AX = 2055 by CL = 100. u The quotient is AL = 14H (20 decimal) u The remainder is AH = 37H (55 decimal).  UNSIGNED MULTIPLICATION & DIVISION division of unsigned numbers u doubleword/word - the numerator is in AX and DX. u The most significant word in DX, least significant in AX. u The denominator can be in a register or in memory. u After DIV, the quotient will be in AX, the remainder in DX. u The maximum quotient FFFFH.  LOGIC INSTRUCTIONS - SHIFT RIGHT u SHR - logical shift right. u Operand is shifted right bit by bit. u For every shift the LSB (least significant bit) will go to the carry flag. (CF) u The MSB (most significant bit) is filled with 0.  LOGIC INSTRUCTIONS - SHIFT LEFT u SHL - Logical shift left, the reverse of SHR. u After every shift, the LSB is filled with 0. u MSB goes to CF. u All rules are the same as for SHR. 3-11 can also be coded as: Example carp proc near mov cx,0 pop bx mov ax,3 pop ax push ax add cx, ax call carp shl ax,1 add cx,ax push bx ret carp endp  SIGNED NUMBER ARITHMETIC OPERATIONS overflow problem - - +96 is added to +70 and the result according to the CPU is -90. Why? The result was more than AL could handle, because like all other 8-bit registers, AL could only contain up to +127. The CPU designers created the overflow flag to inform the programmer that the result of the signed number operation is erroneous.  SIGNED NUMBER ARITHMETIC OPERATIONS the overflow flag in 8-bit operations u In 8-bit signed number operations, OF is set to 1 if: u There is a carry from D6 to D7 but no carry out of D7. u (CF = 0) u There is a carry from D7 out, but no carry from D6 to D7. u (CF = 1) u In other words, the overflow flag is set to 1 if there is a carry from D6 to D7 or from D7 out, but not both. u If there is a carry both from D6 to D7, and from D7 out, then OF = 0.  SIGNED NUMBER ARITHMETIC OPERATIONS the overflow flag in 8-bit operations u In 8-bit signed number operations, OF is set to 1 if: u There is a carry from D6 to D7 but no carry out of D7. u (CF = 0) u There is a carry from D7 out, but no carry from D6 to D7. u (CF = 1) u In other words, the overflow flag is set to 1 if there is a carry from D6 to D7 or from D7 out, but not both. u If there is a carry both from D6 to D7, and from D7 out, then OF = 0.  STRING AND TABLE OPERATIONS byte/word operands in string instructions The operand can be a byte or a word, distinguished by letters B (byte) & W (word) in the mnemonic. word Example.DATA mov si,offset data1 DATA1 DB 'abcdefghijkl' mov di,offset data2 data2 db 12 dup(?) mov cx,12 ;-------------initializing------------- rep movsb.CODE MOV AH, 4CH MAIN PROC FAR mov ax,@data INT 21H mov ds,ax MAIN ENDP mov es,ax END MAIN cld