CAO Finals Handout PDF - Processor Control Instructions

IT2104 Processor Control Instructions In operating strings longer than a doubleword, the string instructions can be String Manipulation combined with a REP instruction to create...

IT2104 Processor Control Instructions In operating strings longer than a doubleword, the string instructions can be String Manipulation combined with a REP instruction to create a repeating instruction. The number Strings are continuous series of bits, bytes, words, or doubleword, stored in of iterations, corresponding to the number of string elements to be operated sequential memory locations. Strings are used to hold any type of information, on, is in the ECX register. String manipulation instructions can begin at higher such as characters and signed numbers. With the implementation of string addresses and work toward lower ones, and vice versa. instructions, the size of a program can be considerably reduced. Generally, string instructions facilitate the following operations: Details of some Emu8086 string instructions: Storing of characters in a string Instruction Description Algorithm Moving strings of data MOVSB  No operands EDI = ESI Comparing of alphanumeric strings  Copy byte: ESI to EDI if DF = 0 then,  The value of C, Z, S, O, P, and A flags are  SI = SI + 1 Searching for a particular byte or word unchanged.  DI = DI + 1 Copying of strings else,  SI = SI - 1 The operations above may involve large data structures, such as  DI = DI – 1 alphanumeric character strings, that are moved and examined within the memory. The string elements to be operated on are identified with the ESI (the CMPSW  No operands ESI - EDI source string element: SI - source index) and EDI (the destination string  Compare words: EDI from ESI if DF = 0 then, element: DI - destination index) registers (Stallings, 2019). These registers are  The value of C, Z, S, O, P, and A flags  SI = SI + 2 depend on the result of the instruction.  DI = DI + 2 automatically incremented or decremented after each iteration of an instruction else, point to the next element in the string.  SI = SI - 2  DI = DI – 2 Common x86 string instructions: Instruction Description SCASB  No operands AL – EDI MOVSB This instruction moves the string byte addressed by the ESI  Compare bytes: AL from EDI if DF = 0 then, register to the location addressed by the EDI register.  The value of C, Z, S, O, P, and A flags  DI = DI +1 CMPSB This subtracts the destination string byte from the ESI and depend on the result of the instruction. else updates the status of the control flags according to results.  DI = DI – 1 SCASB This subtracts the destination string byte from the contents of the AL register and updates the status of the control flags LODSW  No operands AX = ESI according to results.  Loads word at ESI in AX and updates SI if DF = 0 then, LODSB This instruction loads the source string byte identified by the  The value of C, Z, S, O, P, and A flags are  SI = SI + 2 ESI register into the EAX register. unchanged. else, STOSB This stores the source string byte from the AL register into the  SI = SI – 2 memory location identified with the EDI register REP This instruction is used to repeat a given instruction while the STOSB  No operands EDI = AL ECX register is not zero.  Stores byte in AL into EDI and updates DI if DF = 0 then, REPE/REPZ This instruction is used to repeat a given instruction while the  The value of C, Z, S, O, P, and A flags are  DI = DI + 1 ECX register is not zero and the ZF flag is set. unchanged. else, REPNE/REPNZ This instruction is used to repeat a given instruction while the  DI = DI – 1 ECX register is not zero and the ZF flag is cleared. REP  Chain instruction is involved check_cs: 06 Handout 1 *Property of STI  [email protected] Page 1 of 5  IT2104  Repeats following MOVSB, MOVSW, if CX 0 then, If the result of an arithmetic operation is treated as a signed integer, then LODSB, LODSW, STOSB, STOSW  perform the the overflow flag (OF) indicates a carry or borrow. instructions CX times. following If the result of an arithmetic operation is treated as a BCD, then the  The value of the Z flag depends on the chain auxiliary carry flag (AF) indicates a carry or borrow. result of the instruction instruction  CX = CX – 1  go back to In x86 and many other architectures, status flags are set by arithmetic and check_cx compare instructions. The compare operation in most languages subtracts two else, operands, so as the subtraction operation. The only difference is that a  exit from compare operation only sets the status flag, whereas the subtraction operation REP cycle also stores the result of the subtraction in the destination operand. Note that some architectures also set status flags for data transfer instructions. Examples of string manipulation: The x86 architecture encompasses the 32-bit EFLAGS register that contains Code Comment condition codes and carious mode of bits. The EFLAGS register indicates the mov cx, origin ; set REP counter condition of the processor and helps in controlling operations. It generally mov si, offset source ; SI points to source includes the six (6) condition codes defined in the previous module: the carry, mov di, offset target ; DI points to target rep movsb ; copy bytes parity, auxiliary, zero, sign, and overflow flags. On the other hand, in the 64- bit mode, this register is extended and referred to as the RFLAGS. mov si, offset first ; point SI at source string mov di, offset second ; point DI at destination string In addition, the following bits are associated with the operating mode of a cld ; DF is cleared so SI and DI will auto-increment processor: mov cx, 100 ; allocate number of string elements in CX Nested Task Flag – This indicates if the current task is nested within repe cmpsb ; repeat the comparison of string bytes until the end of another task in protected mode. ; string or until compared bytes are not equal Virtual Mode Flag – This allows programmers to enable or disable a mov di, offset string ; put offset of string into DI virtual 8086 mode, which technically determines whether the processor mov al, 0dh ; byte to be scanned for into AL runs as an 8086 machine. mov cx, 80 ; CX used as element counter Virtual Interrupt Flag / Virtual Interrupt Pending Flag – These flags are cld ; DF is cleared so DI will auto-increment both used in a multitasking environment. repne scasb ; compare bytes in string with byte in AL Common x86 flag manipulation instructions: Instruction Description Flag Manipulation CLC This instruction clears or resets the carry flag to zero: CF = 0. Status flags in operating systems are bits in special registers that may be set CLD This instruction clears or resets the direction flag to zero: DF = 0. by certain operations and used in conditional branch instructions. These allow CLI This instruction clears or resets the interrupt flag to zero: IF = 0. a single arithmetic operation to produce results for three different data types: CMC This instruction takes the complement or inverts the value of the unsigned integers, signed integers, and binary coded decimal (BCD). The carry flag. following conditions may be encountered: STC This instruction sets the value of the carry flag to one: CF = 1. STD This instruction sets the value of the direction flag to one: DF = 1. If the result of an arithmetic operation is treated as an unsigned integer, STI This instruction sets the value of the interrupt flag to one: IF = 1. then the carry flag (CF) indicates an out-of-range condition, either carry or barrow. 06 Handout 1 *Property of STI  [email protected] Page 2 of 5  IT2104 Interrupt Triggers 13 General protection A prohibited access to a memory or a system In computer organization and architecture, an interrupt is a signal that resource was attempted. requests the processor to suspend its current execution and serve the interrupt 14 Page fault The memory management unit issued a that occurred. The processor executes the corresponding interrupt service request to resolve a virtual address. routine (ISR), also known as the interrupt handler, in order to serve the 32 - 255 User-defined These vectors are can be utilized by hardware interrupts or with INT instruction. interrupt. After the execution of the ISR, the processor resumes the execution of the suspended program. (Neha, 2021) Interrupts can either be: If more than one interrupt or exception is pending, the processor provides Hardware interrupt: If the processor receives an interrupt request from services in a predictable order. Note that the location of the vector number an external I/O device. within the table does not reflect any priority. Instead, priority among interrupts o Maskable interrupt – This interrupt can be ignored or delayed for and exceptions is organized into five (5) classes. Class 1 holds the highest some time if the processor is executing a program with higher priority. priority, while Class 5 holds the least priority (Stalling, 2019). This is received on the processor's INTR pin. The processor does not recognize a maskable interrupt unless the interrupt flag (IF) is set. Class 1: Traps on the previous instruction (vector 1) o Non-maskable interrupt – This interrupt can neither be ignored nor Class 2: External interrupts (vectors 2, 32-255) delayed and must be executed immediately by the processor. This is Class 3: Faults from fetching next instruction (vectors 3 and 14) received on the processor's NMI pin. The recognition of this particular Class 4: Faults from decoding the next instruction (vectors 6 and 7) interrupt cannot be prevented. Class 5: Faults on executing an instruction (vectors 0, 4, 5, 8, 10-14, 16, Software interrupt: If the processor receives an interrupt that occurs 17) when a condition is met or when a system call occurs. Below is the detailed sequence of events that takes place when an interrupt Interrupt processing within a processor is considered as a facility provided to occurs and is recognized by the processor (Stallings, 2019): support the overall operation of the operating system. It allows a program to 1. The current stack segment register and the current extended stack be suspended, in order to provide immediate service to a variety of interrupt pointer register are pushed onto the stack if the transfer involves a requests, and later be resumed. Interrupt processing on x86 architecture change of privilege level. requires a corresponding interrupt vector table (IVT). Every type of interrupt 2. The current value of the EFLAGS register is pushed onto the stack. is assigned to an interrupt vector or vector number that is used to index the 3. Both the IF and TF are cleared. interrupt vector table. This table contains 256 32-bit interrupt vectors that 4. The current code segment (CS) pointer and the current instruction correspond to specific addresses of different ISR that requires a segment and pointer (IP) are pushed onto the stack. an offset pointer (Stallings, 2019). 5. If the interrupt is accompanied by an error code, then the error code is pushed onto the stack. The table below shows the summary of the interrupt and execution types 6. The interrupt vector contents are fetched and loaded into the CS and available in x86 processors running in protected mode (Ledin, 2020): IP registers. Vector Description Cause 7. Then, the execution continues from the ISR. 0 Divide error A DIV or IDIV instruction attempted an integer 8. To resume the suspended process from the point of interruption, the division by zero. IRS executes an IRET instruction that restores all the values saved on 2 Non-maskable The NMI hardware signal was asserted. the stack. interrupt 3 Breakpoint The INT3 instruction was executed. 6 Invalid opcode An attempt was made to execute a reserved opcode. 06 Handout 1 *Property of STI  [email protected] Page 3 of 5  IT2104 The following are the specific instructions involved when an interrupt request AL = access and sharing int 21h occurs during program execution: modes: Instruction Description mov al, 0 ; read jc err INT This instruction is used to interrupt program execution at a specific mov al, 1 ; write mov handle, ax point in the program. mov al, 2 ; read/write jmp k INTO This instruction is used to interrupt program execution if OF is filename db "myfile.txt", 0 equal to 1. DS:DX → ASCIZ handle dw ? IRET This instruction is used to return from an interrupted service to the filename main program. err: Return: ;.... CF clear is successful, Some of the supported interrupt functions of Emu8086: AX = file handle. k: Instruction Description Examples CF set on error, AX = ret INT 10h / AH = 01h This sets the text-mode ; hides the blinking cursor: error code. cursor. mov ch, 32 mov ah, 1 Notes: Input: int 10h File pointer is set to the CH = cursor start line start of the file. (bits 0-4) and options ; shows a box-shaped blinking File must exists. (bits 5-7) cursor: CL = bottom cursor line mov ch, 0 INT 21h / AH = 39h This creates a directory. ; creates the directory (bits 0-4) mov cl, 7 c:\emu8086\vdrive\C\mydir mov ah, 1 Entry: when run by the emulator: int 10h DS:DX → ASCIZ org 100h pathname; zero mov dx, offset filepath INT 10h / AH = 0Ch This changes the color of mov al, 13h terminated string mov ah, 39h a single pixel. mov ah, 0 int 21h int 10h ; set graphics video Return: Input: mode CF clear if successful, ret AL = pixel color mov al, 1100b AX destroyed. CX = column mov cx, 10 CF set on error AX = filepath DB "C:\mydir", 0 DX = row mov dx, 20 error code. end mov ah, 0ch int 10h ; sets the pixel Note: INT 21h / AH = 2 This writes character to a ; after the execution of AL = All directories in the standard output. DL: given path must exist mov ah, 2 except the last one. Entry: mov dl, 'a' DL = character to write int 21h Generally, hardware interrupts allow processors to respond promptly to INT 21h / AH = 3Dh This opens an existing org 100h requests for services from peripheral devices. It notifies the processor of a file. mov al, 2 need to take some specific action, usually involving data transfer to or from an mov dx, offset filename external device (Ledin, 2020). Entry: mov ah, 3dh 06 Handout 1 *Property of STI  [email protected] Page 4 of 5  IT2104 Aside from interrupts, exceptions can also cause an x86 architecture to suspend execution of the current instruction stream and respond to a program interruption. An exception is generated from the software, which is triggered by the execution of a specific instruction. Exceptions can either be (Stallings, 2019): Processor-detected exceptions – These exceptions occur when the processor encounters an error while attempting to execute an instruction. Programmed exceptions – These are instructions that generate an exception. Some of these instructions are INTO, INT, INT3, and BOUND. Interrupt processing and exception processing rely on the same or similar processor hardware resources, operating in much the same manner. The key difference between the two is that exceptions generally involve responding to conditions arising internal to the processor. Intentionally generating exceptions is considered as a standard method used by unprivileged code to request system services provided by privileged code in the operating system kernel and device drivers. Note that exceptions also utilize the IVT to determine the appropriate response (Ledin, 2020). References: Ledin, J. (2020). Modern computer architecture and organization. Packt Publishing Stallings, W. (2019). Computer organization and architecture: Designing for performance (11th ed.). Pearson Education, Inc. Neha T. (2021, March 19). Interrupts in computer architecture. Retrieved on November 25, 2021 from https://binaryterms.com/interrupts- in-computer-architecture.html 06 Handout 1 *Property of STI  [email protected] Page 5 of 5