Verilog, FPGA PDF

Introduction to Verilog  Verilog Verilog HDL allows a hardware designer to describer designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i.e., gate and switch levels). Verilog languag...

Introduction to Verilog  Verilog Verilog HDL allows a hardware designer to describer designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i.e., gate and switch levels). Verilog language provides the digital designer a software platform. A program tool can convert the Verilog program to a description that was used to make chip, like VLSI. Dr Ramya S ,E & C Dept, MIT, Manipal  VHDL vs. Verilog History Developed by DoD (Department 1983 -Gateway founded by of Defense) in early 80s as means Genrad’s HDL and HILO simulator for Contractors to Describe author. Releases Verilog HDL and Designs-Funded VHSIC Simulator 1987 IEEE ratified 1076 and DoD 1985 Enhanced Verilog-XL-used mandated VHDL(F-22) and EDA for high end designs -Fast vendors created tools. Simulator - interpretive-no need 1993 - IEEE 1076 ‘93 to precompile 1996 Commercial Sim and 1990 Cadence buys Gateway- Synthesis tools become available nearly all ASIC foundries used XL and 1164 pkg enables multi value as Golden Simulator logic 1995 IEEE 1364 Dr Ramya S ,E & C Dept, MIT, Manipal  Lexical Convention Lexical convention are close to C++. Verilog contains a stream of tokens. Tokens can be comments, delimiters, numbers, strings, identifiers, and keywords. Keywords are lower case letter. - The language is case sensitive Dr Ramya S ,E & C Dept, MIT, Manipal  Lexical Convention Numbers are specified in the traditional form or below. b 0 h d (binary octal nexa, , , - , , , decimals Example : 347 // decimal number 4’b101 // 4- bit binary number 0101 2’o12 // 2-bit octal number 5’h87f7 // 5-bit hex number 087f7 - 2’d83 // 2-bit decimal number String in double quotes “ this is a introduction” Dr Ramya S ,E & C Dept, MIT, Manipal  X or Z Values Verilog has two symbols for unknown and high impedance values. These values are very important for modeling real circuits. An unknown value is denoted by an x. A high impedance value is denoted by z. 12'h13x // This is a 12-bit hex number; 4 least significant bits unknown - 6'hx // This is a 6-bit hex number 32'bz // This is a 32-bit high impedance number An x or z sets four bits for a number in the hexadecimal base, three bits for a number in the octal base and one bit for a number in the binary base. If the most significant bit of a number is 0, x, or z, the number is automatically extended to fill the most significant bits, respectively, with 0, x, or z. This makes it easy to assign x or z to whole vector. If the most significant digit is 1, then it is also zero extended Dr Ramya S ,E & C Dept, MIT, Manipal  Identifiers An identifier consists of a sequence of characters that can be letters, digits, $, or underscore ( _ ). The first character of an identifier must be a letter or an underscore. The $ character is reserved for system tasks. Identifiers are case sensitive e.g. Clock and clock are different identifiers An identifier can contain up to 1024 characters; however, the first character cannot be a digit The backslash and whitespace are not part of the identifier. Dr Ramya S ,E & C Dept, MIT, Manipal keyword Many more Keyword….. Dr Ramya S ,E & C Dept, MIT, Manipal  Operators ↳ unary binary , , ternary Operators are of three types: unary, binary, and ternary. Unary operators precede the operand. Binary operators appear between e two e operands. Ternary operators have => two separate operators that separate three operands. a = ~ b; // ~ is a unary operator. b is the operand a = b && c; // && is a binary operator. b and c are operands a = b ? c : d; // ?: is a ternary operator. b, c and d are operands Dr Ramya S ,E & C Dept, MIT, Manipal  Bit wise logical operator ~ bit-wise NOT & bit-wise AND | bit-wise OR ^ bit-wise XOR Dr Ramya S ,E & C Dept, MIT, Manipal  Three Modeling Styles in Verilog SD B Structural modeling (Gate-level) predefined hassign always Use predefined or user-defined primitive gates. Dataflow modeling Use assignment statements (assign) Behavioral modeling Use procedural assignment statements (always) Dr Ramya S ,E & C Dept, MIT, Manipal  Module Module is a basic building block in Verilog. A module definition always begins with the keyword module. The module name, port list, port declarations, and optional parameters must come first in a module definition. Port list and port declarations are present only if the module has any ports to interact with the external environment. The five components within a module are: variable declarations, dataflow statements, instantiation of lower modules, behavioral blocks, and tasks or functions. The endmodule statement must always come last in a module definition. All components except module, module name, and endmodule are optional and can be mixed and matched as per design needs. Verilog allows multiple modules to be defined in a single file. The modules can be defined in any order in the file. Dr Ramya S ,E & C Dept, MIT, Manipal  Program structure module (< port list>); < declares> [semicolon present] endmodule Module name an identifier that uniquely names the module. Port list a list of input, inout and output ports which are referenced in other modules. Dr Ramya S ,E & C Dept, MIT, Manipal  Program structure module (< port list>); < declares> endmodule Declares section specifies data objects as registers, memories and wires as well as procedural constructs such as functions and tasks. Module items initial constructs, always constructs ,assignment. Dr Ramya S ,E & C Dept, MIT, Manipal  Comments //This is a single-line comment on a dedicated line Multiple line comments cannot be nested Dr Ramya S ,E & C Dept, MIT, Manipal  Structural model //structural model of a NAND gate // program nand2.vnot a nomenclature - Reyword , module my_NAND(A, B, F); G input A, B; F keymad output F; nand G(F, A, B); // first parameter must be output. endmodule Dr Ramya S ,E & C Dept, MIT, Manipal  ip and op declared in module block for //Example 3 simplicity· ↑ easier module decoder_gl (input A,B,E, output [0:3] y); g1 Anot g4 wire Anot, Bnot; A not g2 Brot B Og1 (Anot, A), g4 Og2 (Bnot, B); not gates and ↓ g6 g4 (y, Anot, Bnot, E), g5 (y, A,Bnot, E), g7 g6 (y, Anot, B, E), g7 (y, A, B, E); E endmodule not called. > gates are - Dr Ramya S ,E & C Dept, MIT, Manipal  Modeling Circuit Delay This is for simulation only (not for synthesis) Timescale directive indicates units of time for simulation  ‘timescale 1ns / 100ps  #(30) indicates an input to output delay for gate g1 of 30 ns #(10) indicates an input to output delay for gate g2 of 10 ns Dr Ramya S ,E & C Dept, MIT, Manipal  //HDL Example 2 //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; delay is put right and #(30) g1(e,A,B); variable after gate not #(10) g2(y,C); & name. before gate or #(20) g3(x,e,y); endmodule Dr Ramya S ,E & C Dept, MIT, Manipal  Represent Halfadder (A,B,S,Cout) Fulladder(A,B,Cin,S,Cout) Dr Ramya S ,E & C Dept, MIT, Manipal  Half Adder using structural modeling module HA (input A,B, output Sum, Cout); A xor (Sum, A,B); Sum B and(Cout,A,B); Endmodule Cout Dr Ramya S ,E & C Dept, MIT, Manipal  Full Adder module FA( input X1, X2, Cin, output S, Cout ); wire a1, a2, a3; xor u1(a1,X1,X2); and u2(a2,X1,X2); and u3(a3,a1,Cin); or u4(Cout,a2,a3); xor u5(S,a1,Cin); endmodule Dr Ramya S ,E & C Dept, MIT, Manipal Dr Ramya S ,E & C Dept, MIT, Manipal Limitations  Data Flow Modeling ↳ has assign => //Example 1 Nand Gate module my_NANDdfm(A, B, F); G input A, B; F output F; - not needed &wire A,B,F; operator F can be used as an assign F=~(A&B); - > endmodule Dr Ramya S ,E & C Dept, MIT, Manipal  Example 2 Decoder · no need to name gates. module decoder_df (output [0:3] y, input A, B,E); assign y = (~A & ~B & E), y = (A & ~B & E), module decoder_gl (input A,B,E, output [0:3] y); wire Anot, Bnot; y = (~A & B & E), not y = (A & B & E); n1 (Anot, A), endmodule n2 (Bnot, B); and A n4 (y, Anot, Bnot, E), n5 (y, A,Bnot, E), B n6 (y, Anot, B, E), n7 (y, A, B, E); endmodule E Dr Ramya S ,E & C Dept, MIT, Manipal  Data Flow Modeling Represent Halfadder (A,B,Sum,Cout) Fulladder(A,B,Cin,Sum,Cout) Dr Ramya S ,E & C Dept, MIT, Manipal  HalfAdder module HA_df (Sum, Cout, A, B); output Sum,Cout; input A, B; rexor assign Sum = (A ^B), Cout = (A &B); endmodule module HA_df (output Sum, Cout, input A, B); module HA (input A,B, output Sum, Cout); assign Sum = A ^B, xor (Sum, A,B); Cout =A &B; and (Cout,A,B); endmodule Endmodule Dr Ramya S ,E & C Dept, MIT, Manipal  Full Adder module FA_df1( input X1, X2, Cin, output S, Cout ); assign Sum = (A ^ B ^ Cin), Cout = (((A ^B) & Cin) | (A & B)); ↳ AB + CinCAtB) endmodule module FA( input X1, X2, Cin, output S, Cout ); wire a1, a2, a3; xor u1(a1,X1,X2); and u2(a2,X1,X2); and u3(a3,a1,Cin); or u4(Cout,a2,a3); xor u5(S,a1,Cin); endmodule Dr Ramya S ,E & C Dept, MIT, Manipal  Full Adder module FA_df2( input X1, X2, Cin, output S, Cout ); assign S = X1 ^ X2 ^ Cin, Cout = (X1 & X2) | (X2 & Cin) | (X1 & Cin); endmodule Or module FA_df3( input X1, X2, Cin, output S, Cout ); assign {Cout, S} = A + B + Cin; endmodule Dr Ramya S ,E & C Dept, MIT, Manipal Introduction to Verilog Behavioral modeling  Verilog Behavioral Language Structures procedures for sequential or concurrent execution Explicit control of the time of procedure activation specified by both delay expressions and by value changes called event expressions Explicitly named events to trigger the enabling and disabling of actions in their procedures Procedural constructs for conditional, if-else, case, and looping operations Arithmetic, logical, bit-wise, and reduction operators for expressions Procedures called tasks that can have parameters and non-zero time durations Procedures called functions that allow the definition of new operators Dr Ramya S ,E & C Dept, MIT, Manipal  Behavioral modeling The highest level of abstraction in the Verilog HDL Most of the behavioral modeling is done using two important constructs: ❖initial ❖always. All the other behavioral statements appear only inside these two structured procedure constructs. Dr Ramya S ,E & C Dept, MIT, Manipal  initial The statements which come under the initial construct constitute the initial block. e at time 0. & The initial block is executed only once in the simulation, If there is more than one initial block, then all the initial blocks are executed concurrently. The initial construct is used as follows: Example 1 Example 2 initial initial S begin reset = 1’b0; needed when code reset = 1'b0; initial 1 clk = 1'b1; is longer than & end line Dr Ramya S ,E & C Dept, MIT, Manipal  always The statements which come under the always construct constitute the always block. The always block starts at time 0, and keeps on - executing all the simulation time. G - It works like a infinite loop. It is generally used to model a functionality that is continuously repeated. always - Every 5ns , cluck> - cock #5 clk = ~clk; Edelay initial clk = 1'b0; Dr Ramya S ,E & C Dept, MIT, Manipal  always ↓ change in always @(b,c,d) L list begin ↳ sensitivity a = ( b + c )*d; e = b | c; end whenever there is a change in b, c, or d the always block will be executed. Here the list b, c, and d is called the sensitivity list. Dr Ramya S ,E & C Dept, MIT, Manipal  Procedural assignments Used for updating reg, integer, time, real, realtime, and memory data types. The variables will retain their values until updated by another procedural assignment. The LHS of a procedural assignment could be: reg, integer, real, realtime, or time data type or Memory word. Dr Ramya S ,E & C Dept, MIT, Manipal  Procedural assignments Two types : blocking and non-blocking assignments. Blocking assignments: ❖ A blocking assignment statements are executed in the order they are specified in a sequential block. ❖ The execution of next statement begin only after the completion of the present blocking assignments. ❖ A blocking assignment will not block the execution of the next statement in a - parallel block. The blocking assignments are made using the operator =. initial begin a = 1; - b = #5 2; & time c =O #2 3; end 2 572 = 7 unit - In the above example, a is assigned value 1 at time 0, and b is assigned value 2 at time 5, and c is assigned value 3 at time 7. Dr Ramya S ,E & C Dept, MIT, Manipal  Non-blocking assignments: ❖ The non blocking assignment allows assignment scheduling without blocking the procedural flow. ❖ The non blocking assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other. ❖ Non-blocking assignments are made using the operator