HDL Construction3.pdf

HDL Constructs The original Verilog standard (IEEE 1364) has been module Example updated numerous times since its creation in 1995. (output wire F, The most significant update occurred in 2001, which input wire A,B,C);...

HDL Constructs The original Verilog standard (IEEE 1364) has been module Example updated numerous times since its creation in 1995. (output wire F, The most significant update occurred in 2001, which input wire A,B,C); wire An; //internal wires was titled IEEE 1394-2001. In 2005 minor corrections assign An = !A; //behavior desc. and improvements were added to the standard, which assign F = (An && B) || C; endmodule resulted in IEEE 1394-2005. (LaMeres, 2019) A Verilog design describes a single system in a single file. The file has the suffix *.v. Within the file, the system description is contained within a module. The module includes the interface to the system (i.e., the inputs and outputs) and the description of the behavior. Verilog / Pseudocode Logic Diagram Ports and(f,x1,x2); Input: f f = x1 AND x2 Output: x1, x2 or(f,a,b,c,d,e); Input: f f = a OR b OR c OR d or e Output: a, b, c, d & e not(y,x); Input: X y = NOT x Output: Y Verilog Assignments (Mathys, 2014) Structural Description – this description of a digital circuit consists of the interconnection of basic circuit elements like logic gates. Verilog includes basic gate-level primitives. A logic circuit is specified in the form of a module with inputs and outputs (ports) and statements that define the circuit. Note: Do not forget to add a semicolon (;) at the end of each expression. Example: Half Adder – adds two bits “a” and “b” and produces sum “s” and carry “c”. Verilog Code Logic Diagram Truth Table module HalfAdd_Struct1(a,b,c,s); input a,b; //input ports output c,s; //output ports a b c s wire an,bn; //internal wires wire u,v; 0 0 0 0 not(an,a); //struct desc. not(bn,b); 0 1 0 1 and(u,an,b); and(v,a,bn); 1 0 0 1 or(s,u,v); 1 1 1 0 and(c,a,b); endmodule Example: Half Adder using NAND implementation. Verilog Code Logic Diagram Notes module HalfAdd_Struct2(a,b,c,s); Note: Module names input a,b; //inputports must start with a letter output c,s; //outputports wire u,v; //wires followed by any letters or wire cn; numbers plus underscore nand(u,~an,b); //nand (_) or a dollar sign ($). nand(v,a,~b); //~negation In some cases, the tilde nand(s,u,v); (~) symbol can also nand(cn,a,b); nand(c,cn,cn); represent bit negation endmodule instead of using not gate.  Continuous Assignments - This is used to assign values onto wire a,b,c; scalar and vector nets that whenever the signal on the RHS assign a = b & c; (Right-hand-side) changes, the LHS (Light-hand-side) will be LHS = RHS reevaluated. Note: Whenever variable “b” or “c” (in o Nets – It represents structural connections between the LHS) changes, variable “a” (RHS) is components/hardware elements. updated instantly. Example: Half Adder via Continuous Assignment Verilog Code Notes module HalfAdd_Behave1(a,b,c,s); Note: input a,b; //inputports Ampersand (“&”) – represents AND output c,s; //outputports Vertical Bar (“|”) – represents OR assign s = (~a&b)|(a&~b); Tilde (“~”) – represents NOT assign c = a&b; endmodule Procedural Assignments – It is computed as some point in time (ex: A clock) then has reg [7:0] data; to get stored in a memory element. Rather than specifying conditional expressions, integer count; procedural statements (if-else, case, while, for statements) as a higher level of real period; abstraction are used. o Registers - represent variables used to store data. It retains value until another value is placed. Example: Half Adder via Procedural Assignment. Verilog Code Notes Note: module HalfAdd_Behave2(a,b,c,s); input a,b; //inputports If-else statements are conditions that are needed to output reg c,s; //using register be satisfied in order to run a specific code block. o != – refers to not equal in statements. always @(a,b) begin //procedure if(a!=b) //!=(not equal) reg is the command used to store a particular data s = 1; temporarily or until it is replaced. else An always block can contain a single/multiple s = 0; statement/s. Triggers input-sensitivity. c = a&b; o begin – used to start the procedure. end c = a&b; endmodule o end – used to end the procedure. A module can contain several always blocks. Hierarchical Assignments – It is composed of the top-level module and several instances of lower-level modules which may contain sub-modules. o Lower-level modules are instantiated in a higher-level module. The output of a lower-level module, as seen by the higher-level module, is a continuous assignment to a net. It implies that modules cannot be instantiated inside a procedural block such as the always block. Example: Full-Adder from Half-adders. Logic Block Diagram Truth Table Cin x y Cout S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1  Verilog Code (Half-Adder – Lower Module) Verilog Code (Full-Adder – Higher Module) module FullAdd(cin,x,y,cout,s); module HalfAdd(a,b,c,s); input cin; //carry input input a,b; //inputports input x,y; output c,s; //outputports output cout; //carry output wire u,v; //wires output s; wire cn; wire c1,c2,s1; //wires assign s = a^b; //^ means XOR HalfAdd HA1 (x,y,c1,c2); //INSTATATION-1 assign c = a&b; HalfAdd HA2 (s1,cin,c2,s); // INSTATATION-2 endmodule assign c = a&b; endmodule Data Types (LaMeres, 2019) In Verilog, every signal, constant, variable, and function must be assigned a data type. The Value Description IEEE 1394-2005 standard provides a variety of pre-defined data types. Logic Zero / 0 Variable Data Types – These data types model storage. Variable data types will hold False the value assigned to them until their next assignment. 1 Logic One / True Type Description Unknown / X reg Logic Storage - 0,1,X & Z Uninitialized integer 32-bit variable whole numbers between + and - 2,147,483,684 Tristated / High Z Impedance real 64-bit floating point variable between - and + 2.2x10^308 time Unsigned 64-bit values from 0 to 9.2x10^18 realtime Same as time but for readability Vector – It refers to a one-dimensional array of elements. All of the net data types, in addition to the variable type reg, can be used to form vectors. While any range of indices can be used, it is common practice to have the LSB index start at zero. Example: wire [7:0] Sum; // 8-bit vector “Sum” with indexes MSB=7 and LSB=0. reg [15:0] Q; // 16-bit vector “Q” of type reg. Sum; // The least significant bit of the vector “Sum”. Array - It refers to a multidimensional array of elements. This can also be thought of as a “vector of vectors.” Vectors within the array all have the same dimensions. Example: Mem[0:4095]; // Defines an array of 4096, 8-bit vectors of type reg. integer A[1:100]; // Defines an array of 100 integers. Mem; // This is the 3rd element within the array named “Mem”. Mem; // This is the MSB of the 3rd element within the array “Mem”. Expressing Numbers Using Different Bases - If a number is simply entered into Verilog without identifying syntax, it is treated as an integer. Verilog supports defining numbers on other bases. Syntax Description ‘b Unsigned binary Example: ‘o Unsigned octal 10 // This is treated as decimal 10 (32-bit signed). 4’b1111 // A 4-bit number with the value 1111(BASE 2). Unsigned ‘d 8’b1011_0000 // An 8-bit number with the value 10110000(BASE 2). decimal 8’hFF // An 8-bit number with the value 11111111(BASE 2). Unsigned 8’hff // An 8-bit number with the value 11111111(BASE 2). ‘h hexadecimal 6’hA // A 6-bit number with the value 001010(BASE 2). ‘sb Signed binary 8’d7 // An 8-bit number with the value 00000111(BASE 2). ‘so Signed octal 32’d0 // A 32-bit number with the value 0000_0000(BASE 16). ‘sd Signed decimal ’b1111 // A 32-bit number with the value 0000_000F(BASE 16). Signed 8’bZ // An 8-bit number with the value ZZZZ_ZZZZ. ‘sh hexadecimal  Parameter - A parameter, or constant, is useful for representing a quantity that will be used multiple times in the architecture. Note: the type is optional and can only be integer, time, real, or real-time. If a type is provided, the parameter will have the same properties as a variable of the same time. If the type is excluded, the parameter will take on the type of the value assigned to it. Example: parameter BUS_WIDTH = 64; parameter NICKEL = 8’b0000_0101; Compiler Directive – It provides additional information to the simulation tool on how to interpret the Verilog model. A compiler directive is placed before the module definition and is preceded with a backtick (i.e., `). Note: It is not an apostrophe. `include This lets you insert the entire contents of a source file into another file during Verilog compilation. You can use the `include compiler directive to include global or commonly-used definitions and tasks, without encapsulating repeated code within module boundaries. `define This compiler directive is used for defining text MACROS. Since `define is a compiler directive, it can be used across multiple files. `timescale , This defines the timescale of the delay unit and its smallest precision. `defaultnettype This allows the user to override the ordinary default type (wire) of implicitly declared nets. It must be used outside a module. Example: ‘timescale 1ns/1ps Declares the unit of time is 1 ns with a precision of 1ps The precision is the smallest amount that the time can take on. For example, with this directive, the number 0.001 would be interpreted as 0.001 ns or 1 ps. However, the number 0.0001 would be interpreted as 0 since it is smaller than the minimum precision value. References: Cavanagh, J. (2016). Sequential logic and Verilog HDL design examples. CRC Press. LaMeres, B. (2019). Introduction to logic circuits & logic design with Verilog (2nd ed.). Springer. Li, Y. (2015). Computer principles and design in Verilog HDL. Wiley. Mano, M. & Ciletti, M. (2017). Digital design with an introduction to the Verilog HDL, VHDL, and SystemVerilog (6th ed.). Pearson. Mathys, P. [Peter Mathys]. (2014, September 6). Introduction to Verilog part 1 [Video]. YouTube. https://www.youtube.com/watch?v=0age83XI8Z4 Mathys, P. [Peter Mathys]. (2014, September 6). Introduction to Verilog part 2 [Video]. YouTube. https://youtube.com/watch?v=IREjtgG33hQ Verilog Assignments. (n.d.). In Javatpoint.com. Retrieved on 2021, February 8 from https://www.javatpoint.com/verilog- assignments