Verilog HDL Basics Quiz

Introduction to Verilog

• Verilog HDL allows hardware designers to describe designs at a high level of abstraction (architectural or behavioral) and lower implementation levels (gate and switch).
• Verilog language provides a software platform for digital designers.
• A program tool can convert Verilog programs into descriptions used to create chips (e.g., VLSI).

VHDL vs. Verilog History

• VHDL was developed by the DoD in the early 80s for contractors to describe designs-funded VHSIC.
• IEEE ratified the 1076 standard and DoD mandated VHDL (F-22) in 1987, and EDA vendors created tools.
• Gateway, founded in 1983, developed the Verilog HDL and simulator.
• Enhanced Verilog-XL (1985) was used for high-end designs.
• Cadence acquired Gateway in 1990, leading to wider use of Verilog-XL as the industry standard.
• IEEE 1364 (1995) defined the standard for Verilog HDL.

Lexical Convention

• Verilog's lexical conventions are similar to C++.
• Verilog consists of tokens (comments, delimiters, numbers, strings, identifiers, and keywords).
• Keywords are lowercase.
• Verilog is case-sensitive.

Lexical Convention - Numbers

• Numbers are specified traditionally.
• (e.g., 347 // decimal, 4'b101 // 4-bit binary, 2'o12 // 2-bit octal, 5'h87f7 // 5-bit hex, 2'd83 // 2-bit decimal).
• Strings are enclosed in double quotes (e.g., “this is a string”).
• Base formats include b (binary), 0 (octal), h (hex), d (decimal).

X/Z Values

• Verilog uses x for unknown and z for high-impedance values in circuit modeling.
• 12'h13x // 12-bit hex with four unknown least significant bits
• 6'hx // 6-bit hex number with all bits unknown
• 32'bz // 32-bit high impedance number.
• X or Z extend to fill the most significant bits with 0, x, or z if needed.

Identifiers

• An identifier is a sequence of characters (letters, digits, $, _).
• Identifiers must start with a letter or an underscore (_).
• The $ character is reserved for system tasks.
• Identifiers are case-sensitive (e.g., Clock and clock are different identifiers).
• Backslashes and whitespace are not part of identifiers.
• Identifiers can have up to 1024 characters; however, the first character cannot be a digit.

Operators

• Operators are unary (precede operand), binary (between two operands), or ternary (two operators separating three operands).
• Examples:
  • Unary: ~ (bit-wise NOT)
  • Binary: && (logical AND), || (logical OR)
  • Ternary: ?:

Bitwise Logical Operators

• ~: bit-wise NOT
• &: bit-wise AND
• |: bit-wise OR
• ^: bit-wise XOR

Three Modeling Styles in Verilog

• Structural (Gate-level): Uses predefined or user-defined primitive gates.
• Dataflow: Uses assignment statements (e.g., assign).
• Behavioral (Procedural): Uses procedural assignment statements (e.g., always).

Module

• A module definition begins with the keyword module.
• The module name, port list, and port declarations must come first, optionally followed by parameters.
• A module can interact with an external environment through ports.
• Modules contain declarations, dataflow statements, instantiation of lower-level modules, and tasks or functions.
• The endmodule statement marks the end of the module.
• Optional components can be mixed and matched.

Program Structure

• module <module_name> (<port_list>);
• <declarations>
• <module_items>
• endmodule
• Describes the module's components (inputs, outputs, variables, etc.).
• Declares data objects (registers, memories, wires) and procedural constructs (functions, tasks).

Comments

• Single-line comments start with //.
• Multi-line comments start and end with /* */.
• Multiple-line comments cannot be nested.

Structural Model Example

• Example of a NAND gate implementation in Verilog, including input, output, and the nand gate primitive.

Data Flow Modeling Example

• Example of a NAND gate implementation in Verilog using assignment statements.

Data Types

• Values: 0 (logic zero), 1 (logic one), x (unknown), z (high impedance)
• Registers: Store values between assignments
• Nets: Physical connections carrying signals
• Memories: Arrays of memory locations
• Integers, Reals, and Times: Data types for numeric values.

Procedural Assignments (Blocking/Non-Blocking)

• Blocking assignments (=): Execute in order. Next statement begins only after the current blocking assignment completing.
• Non-blocking assignments (<=): Execute concurrently; assignments scheduled, not in order of appearance.

Conditional Statements (if-else)

• if (condition): Executes statement if condition is true.
• else if (condition): Executes statement if previous conditions have not been true, but the current one is.
• else: Used for executing a statement if none of the preceding conditions are true.
• begin ...end: Used to group statements within a conditional block.

Case Statement

• Evaluates an expression against different cases.
• Executes the statement associated with the matching case.
• default: Executes if no case matches.

Loop Statements

• forever: Loop that executes continuously
• repeat: Repeats a block a specified number of times.
• while: Loops while a condition is true.
• for: Loops a specific number of times.

Behavioral Modeling

• The highest level of abstraction in Verilog.
• Behavioral descriptions use procedural statements like always and initial.
• initial blocks execute only once (at time zero).
• always blocks continuously execute whenever any of the variables listed in the sensitivity list change.

Identifiers, Keywords

• Keywords in Verilog refer to predefined Verilog words like 'module' which are reserved and cannot be used as identifiers, or names for variables, circuits, or modules.
• Identifiers must be valid Verilog names

Operators

• Verilog provides operators for performing logical, arithmetic, bitwise, and reduction operations in Verilog HDL.

Modules (Verilog)

• Modules in Verilog are a building block of hardware designs.

Data Types: Registers

• A data type in Verilog that describes a storage cell to hold a value, and can be a scalar or a vector (with multiple bits)

Data Types: Nets

• In Verilog HDL a net is a connection that connects two or more data elements such as gates or memory or registers

Types of Logic Modules

• C-Modules, S-Modules

Implementing Logic Functions

• Methods such as Using Shannon's Expansion Theorem to reduce the complexity of a logic function
• Using dataflow modeling for a logic function
• Using UDP to perform logic operations
• Using if/else conditional statements to perform logic operations
• Using case statements to perform logic operations
• Using loop statements to perform logic operations
• Using Boolean operators to design logic modules

Implementing Sequential Logic Functions (D Flip-flop, JK Flip-flop, Counters, Shift registers)

• Methods for implementing sequential logic functions like D Flip-flop, JK Flip-flop, Counters and Shift registers in Verilog HDL, using sequential statements.

FPGA Architecture

• FPGA architectures use logic blocks, programmable interconnect switches, I/O blocks and other logic elements.

Logic Block Types

• Look-up Table(LUT) based, or MUX based.

FPGA Features

• Commercially available FPGAs generally use Static RAM, Antifuse, EPROM, Static RAM, and EEPROM for programming.

Shannon's Expansion Theorem

• Used to expand logical functions written using Boolean variables.

ASICs

• Application Specific Integrated Circuits
• Designed for very particular applications, as opposed to general purpose integrated circuits
• Not software programmable

ASIC Design Flow

• A sequence of steps in the design of an ASIC.

PLDs, PLAs, PROMs

• Programmable Logic Devices are integrated circuits (IC's) with a configurable structure used to create logic circuits.
• Programmable Logic Arrays (PLAs) use both AND and OR arrays to realize a logic function.
• Programmable Read-Only Memories (PROMs) are used to implement logic functions that are stored rather than having to be computed in real time.

Data Types

• Types of data used to write Verilog HDL code.

Data Types

• Data types in Verilog.

Additional Topics

• Verilog HDL specifics

Test your knowledge of Verilog HDL with this quiz that covers its primary purpose, lexical conventions, and significant historical standards. Answer questions regarding identifiers, representations of numbers, and the functionality of specific symbols in Verilog.