1_Introduction_to_HDL.pdf

INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE PROGRAMMING Verilog HDL Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware b...

INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE PROGRAMMING Verilog HDL Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits. What is Verilog? Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL), which is used to describe a digital system such as a network switch or a microprocessor or a memory a flip-flop. Verilog was developed to simplify the process and make the HDL more robust and flexible. Today, Verilog is the most popular HDL used and practiced throughout the semiconductor industry. HDL was developed to enhance the design process by allowing engineers to describe the desired hardware's functionality and let automation tools convert that behavior into actual hardware elements like combinational gates and sequential logic. Verilog is like any other hardware description language. It permits the designers to design the designs in either Bottom-up or Top-down methodology.  Bottom-Up Design: The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standards gates. This design gives a way to design new structural, hierarchical design methods. Top-Down Design: It allows early testing, easy change of different technologies, and structured system design and offers many other benefits. Verilog Abstraction Levels Verilog supports a design at many levels of abstraction, such as: o Behavioral level o Register-transfer level o Gate level Behavioral level The behavioral level describes a system by concurrent algorithms behavioral. Every algorithm is sequential, which means it consists of a set of executed instructions one by one. Functions, tasks, and blocks are the main elements. There is no regard for the structural realization of the design. Register-Transfer Level (RTL) Designs using the Register-Transfer Level specify a circuit's characteristics using operations and the transfer of data between the registers. The modern definition of an RTL code is "Any code that is synthesizable is called RTL code". Gate Level The characteristics of a system are described by logical links and their timing properties within the logical level. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (basic gates). Gate level modeling may not be the right idea for logic design. Gate level code is generated using tools such as synthesis tools, and his netlist is used for gate-level simulation and backend. History of Verilog ▪ Verilog HDL's history goes back to the 1980s when a company called Gateway Design Automation developed a logic simulator, Verilog-XL, and a hardware description language. ▪ Cadence Design Systems acquired Gateway in 1989 and with it the rights to the language and the simulator. In 1990, Cadence put the language into the public domain, with the intention that it should become a standard, non-proprietary language.  ▪ The Verilog HDL is now maintained by a nonprofit making organization, Accellera, formed from the merger of Open Verilog International (OVI) and VHDL International. OVI had the task of taking the language through the IEEE standardization procedure. ▪ In December 1995, Verilog HDL became IEEE Std. 1364-1995. A significantly revised version was published in 2001: IEEE Std. 1364-2001. There was a further revision in 2005, but this only added a few minor changes. ▪ Accellera has also developed a new standard, SystemVerilog, which extends Verilog. ▪ SystemVerilog became an IEEE standard (1800-2005) in 2005. How is Verilog useful? Verilog creates a level of abstraction that helps hide away the details of its implementation and technology. For example, a D flip-flop design would require the knowledge of how the transistors need to be arranged to achieve a positive-edge triggered FF and what the rise, fall, and CLK- Q times required to latch the value onto a flop among much other technology-oriented details. Power dissipation, timing, and the ability to drive nets and other flops would also require a more thorough understanding of a transistor's physical characteristics. Verilog helps us to focus on the behavior and leave the rest to be sorted out later. Prerequisites Before learning Verilog, you should have a basic knowledge of VLSI Design language. ▪ You should know how Logic diagrams work, Boolean algebra, logic gates, Combinational and Sequential Circuits, operators, etc. ▪ You should know about Static timing analysis concepts such as setup time, hold time, critical path, limits on clock frequency, etc. ▪ ASIC and FPGA basics and Synthesis and simulation concepts. Lexical Tokens Lexical conventions in Verilog are similar to the C programming language. Verilog language source text files are a stream of lexical tokens. A lexical token may consist of one or more characters, and every single character is in exactly one token. The tokens can be keywords, comments, numbers, white space, or strings. All lines should be terminated by a semi-colon (;). ▪ Verilog HDL is a case-sensitive language. ▪ And all keywords are in lowercase. White Space White space can contain the characters for tabs, blanks, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings. Comments There are two types to represent the comments, such as: 1. Single line comments begin with the token // and end with a carriage return. For example, //this is the single-line syntax. 2. Multi-Line comments begin with the token For example, Numbers We can specify constant numbers in binary, decimal, hexadecimal, or octal format. Negative numbers are represented in 2's complement form. The question mark (?) character is the Verilog alternative for the z character when used in a number. The underscore character (_) is legal anywhere in a number, but it is ignored as the first character. 1. Integer Number Verilog HDL allows integer numbers to be specified as: ▪ Sized or unsized numbers (Unsized size is 32 bits ). ▪ In a radix of decimal, hexadecimal, binary or octal. ▪ Radix and hex digits (a,b,c,d) are case insensitive. ▪ Spaces are allowed between the radix, size, and value. Syntax The syntax is given as: 2. Real Numbers ▪ Verilog supports real constants and variables. ▪ Verilog converts real numbers to integers by rounding. ▪ Real Numbers can not contain 'A' and 'X'. ▪ Real numbers may be specified in either decimal or scientific notation. ▪ < value >.< value > ▪ < mantissa >E< exponent > ▪ Real numbers are rounded off to the nearest integer when assigning to an integer. 3. Signed and Unsigned Numbers Verilog supports both the type of numbers, but with certain restrictions. In C language, we don't have int and unint types to say if a number is signed integer or unsigned integer. Any number that does not have a negative sign prefix is positive. Or indirect way would be "Unsigned". Negative numbers can be specified by putting a minus sign before the size for a constant number, thus become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic. 4. Negative Numbers Negative numbers are specified by placing a minus (-) sign before the size of a number. It is illegal to have a minus sign between base_format and number. Identifiers The identifier is the name used to define the object, such as a function, module, or register. Identifiers should begin with alphabetical characters or underscore characters. For example, A_Z and a_z. Identifiers are a combination of alphabetic, numeric, underscore, and $ characters. They can be up to 1024 characters long. ▪ Identifiers must begin with an alphabetic character or the underscore character (a- z A-Z_). ▪ Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $). ▪ Identifiers can be up to 1024 characters long. Escaped Identifiers Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers are including any of the printable ASCII characters in an identifier. o The decimal values 33 through 126, or 21 through 7E in hexadecimal. o Escaped identifiers begin with the backslash (\). The backslash escapes the entire identifier. o The escaped identifier is terminated by white space characters such as commas, parentheses, and semicolons become part of the escaped identifier unless preceded by white space. o Terminate escaped identifiers with white space. Otherwise, characters that should follow the identifier are considered part of it. Operators Operators are special characters used to put conditions or to operate the variables. There are one, two, and sometimes three characters used to perform operations on variables. 1. Arithmetic Operators These operators perform arithmetic operations. The + and -are used as either unary (x) or binary (z-y) operators. The operators included in arithmetic operation are addition, subtraction, multiplication, division, and modulus. 2. Relational Operators These operators compare two operands and return the result in a single bit, 1 or 0. The Operators included in relational operation are: o == (equal to) o != (not equal to) o > (greater than) o >= (greater than or equal to) o < (less than) o (shift right) 7. Concatenation Operator The concatenation operator combines two or more operands to form a larger vector. The operator included in Concatenation operation is: o { }(concatenation) 8. Replication Operator The replication operator is making multiple copies of an item. The operator used in Replication operation is: o {n{item}} (n fold replication of an item) 9. Conditional Operator Conditional operator synthesizes to a multiplexer. It is the same kind as is used in C/C++ and evaluates one of the two expressions based on the condition. The operator used in Conditional operation is: o (Condition) ? Operands Operands are expressions or values on which an operator operates or works. All expressions have at least one operand. 1. Literals Literals are constant-valued operands that are used in Verilog expressions. The two commonly used Verilog literals are: String: A literal string operand is a one-dimensional array of characters enclosed in double quotes (" "). Numeric: A constant number of the operand is specified in binary, octal, decimal, or hexadecimal number. 2. Wires, Regs, and Parameters Wires, regs, and parameters are the data types used as operands in Verilog expressions. Bit-Selection "x" and Part-Selection "x[4:2]" Bit-selects and part-selects are used to select one bit and multiple bits, respectively, from a wire, regs or parameter vector using square brackets "[ ]". 3. Function Calls In the Function calls, the return value of a function is used directly in an expression without first assigning it to a register or wire. It just places the function call as one of the types of operands. It is useful to know the bit width of the return value of the function call. ASIC Design Flow A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially. Requirements A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed. The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project. Specifications The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as: 1. Requires computational power to run imaging algorithms to support virtual reality. 2. Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz. 3. Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces. 4. It should support 1920x1080 pixel displays with an appropriate controller. Architecture Now, the architect gives a system-level view of how the chip should operate. They will decide what all other components are required, what clock frequencies they should run, and how to target power and performance requirements. They also decide on how the data should flow inside the chip. An example would be the data flow when a processor fetches imaging data from the system ram and executes them. Meanwhile, the graphics engine will execute post-processed data from the previous batch dumped into another part of memory and so on. Digital Design Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused. For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one. It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors. Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL. This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills. Verification Once the RTL design is ready, it needs to be verified for functional correctness. For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected. The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre- silicon verification engineer. To save time and reach functional closure, both the design and verification teams operate in parallel, where the designers release an RTL version. The verification team develops a testbench environment and test cases to test the functionality of that RTL version. If any of these tests fail, it might indicate a problem with the design, and a "bug" will be raised on that design element. This bug will have to be fixed in the next version of the RTL release from the design team. This process goes on until there is a good level of confidence in the design's functional correctness. Logic Synthesis Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis. Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them. Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node processes and digital elements libraries and can make intelligent calculations to meet all these different criteria. These libraries are obtained from semiconductor fabs that provide data characteristics for different components such as rise or fall times for flip-flops, input-output time for combinational gates, etc. Logic Equivalence The gate-level netlist is checked for logical equivalence with the RTL. Sometimes, a gate- level verification is performed where verification of certain elements is done once again, the difference being this time it is at the gate level and a lower level of abstraction. Simulation times tend to be slower because of the huge number of elements involved in the design and back annotated delay information. Placement and Routing Then, the netlist is inputted to the physical design flow, where automatic place and the route are done with EDA tools' help. The Cadence Encounter and Synopsys IC Compiler are good examples of these kinds of tools. This will select and place standard cells into rows, define ball maps for input and output, create different metal layers, and place buffers to meet timing. Once this process is done, a layout is generated and usually sent for fabrication. This stage is usually handled by the physical design team, who are well familiar with the technology node and physical implementation details. Validation A sample chip will be made-up either by the same semiconductor firm or sent to a third- party such as TSMC or Global Foundries. This sample now goes through a post-silicon validation process where another team of engineers runs different tester patterns. It is more difficult to debug in post-silicon validation than pre-silicon verification simply because the level of visibility into a chip's internal nodes is drastically reduced. A million clock cycles would have finished in a second, and tracing back to the exact time of error will be time-consuming. If there are any real issues or design bugs found at this stage, this will have to be fixed in RTL, re-verified, and all the steps that follow this will have to be performed. Even though there are multiple steps in the design flow, a lot of the design activity is usually concentrated on the optimization and verification of the RTL description of the circuit. It is important to note that although EDA tools are available to automate the processes, improper usage will lead to inefficient designs. Hence, a designer has to make conscious choices during the design process. Design Abstraction Layers The Verilog language would be essential to understand the different layers of abstraction in chip design. The top layer is the system-level architecture that defines the various sub-blocks and groups them based on functionality. For example, a processor cluster can have multiple cache blocks, cores, and cache coherence logic. All of this will be represented as a single block with input and output signals. On the next level, each sub-block is written in a hardware description language to describe each block's functionality accurately. Lower-level implementation details such as circuit schematics, technology libraries are ignored at this stage. For example, a controller block will have multiple Verilog files, each describing a smaller functionality component. HDLs are then converted to gate-level schematics that involve technology libraries that characterize digital elements such as flip-flops. For example, the digital circuit for a D latch contains NAND gates arranged in a certain manner such that all combinations of D and E inputs produce an output Q given by the truth table. A truth table essentially gives permutation of all input signal levels and the resulting output level. The hardware schematic can also be derived from the truth table using K-maps and Boolean logic. However, it is not useful to follow this method for more complex digital blocks like controllers and processors. Implementation of a NAND gate is done by the connection of CMOS transistors in a particular format. At this level, the transistor channel widths, Vdd, and the ability to drive the output capacitative load are taken into account during the design process. The final step is the layout of these transistors in silicon using EDA tools to be fabricated. Some device and technology knowledge would be required at this level because different layouts end up having different physical properties like resistance and capacitance, among other implications. Design Styles There are primarily two styles followed in the design of digital blocks, one is top-down, and another is bottom-up methodologies. 1. Top-Down In this methodology, a top-level block is first defined along with identifying sub-modules required to build the top block. Similarly, each sub-blocks is further divided into smaller components, and the process continues until we reach the leaf cell or a stage where it can't be further divided. 2. Bottom-up The first task is to identify the available building blocks. Then put them together and connected in a certain way to build bigger cells and used to piece together the top-level block. We can also use the combination of both flows. Architects define the system-level view of the design, and designers implement each of the functional blocks' logic and get synthesized into gates. A top-down style is followed until this point. However, these gates have been built by following a bottom-up flow, starting with the smallest block's physical layout in the best possible area, power, and performance. These standard cells also have a hardware schematic. And these can be used to obtain various information such as rise and fall in power, times, and other delays. These cells are made available to the synthesis tool, which picks and instantiates them where required. Verilog Data Types Verilog introduces several new data types. These data types make RTL descriptions easier to write and understand. The data storage and transmission elements found in digital hardware are represented using a set of Verilog Hardware Description Language (HDL) data types. In Verilog, data types are divided into NETS and Registers. These data types differ in the way that they are assigned and hold values, and also, they represent different hardware structures. The Verilog HDL value set consists of four basic values: Value Description 0 Logic zero or false 1 Logic one or true X Unknown logical value Z The high impedance of the tri-state gate Integer and Real Data Types Many data types will be familiar to C programmers. The idea is that algorithms modeled in C can be converted to Verilog if the two languages have the same data types. Verilog introduces new two-state data types, where each bit is 0 or 1 only. Using two- state variables in RTL models may enable simulators to be more efficient. And they are not affecting the synthesis results. Types Description bit user-defined size byte 8 bits, signed shortint 16 bits, signed int 32 bits, signed longint 64 bits, signed  ▪ Two-state integer types Unlike in C, Verilog specifies the number of bits for the fixed-width types. Types Description reg user-defined size logic identical to reg in every way integer 32 bits, signed ▪ Four-state integer types We preferred logic because it is better than reg. We can use logic where we have used reg or wire. Type Description time 64-bit unsigned shortreal like a float in C shortreal like double in C realtime identical to real Non-Integer Data Types Arrays In Verilog, we can define scalar and vector nets and variables. We can also define memory arrays, which are one-dimensional arrays of a variable type. Verilog allowed multi-dimensioned arrays of both nets and variables and removed some of the restrictions on memory array usage. Verilog takes this a stage further and refines the concept of arrays and permits more operations on arrays. In Verilog, arrays may have either packed or unpacked dimensions, or both. Packed dimensions o Are guaranteed to be laid out contiguously in memory. o It can be copied on to any other packed object. o Can be sliced ("part-selects").  o Are restricted to the "bit" types (bit, logic, int, etc.), some of which (e.g., int) have a fixed size. Unpacked dimensions It can be arranged in memory in any way that the simulator chooses. We can reliably copy an array on to another array of the same type. For arrays with different types, we have to use a cast, and there are rules for how an unpacked type is cast to a packed type. Verilog permits several operations on complete unpacked arrays and slices of unpacked arrays. For these, the arrays or slices involved must have the same type and shape, i.e., the same number and lengths of unpacked dimensions. The packed dimensions may differ, as long as the array or slice elements have the same number of bits. The permitted operations are: o Reading and writing the whole array. o Reading and writing array slices. o Reading and writing array elements. o Equality relations on arrays, slices, and elements Verilog also includes dynamic arrays (the number of elements may change during simulation) and associative arrays (which have a non-contiguous range). Verilog includes several arrays of querying functions and methods to support all these array types. Nets Nets are used to connect between hardware entities like logic gates and hence do not store any value. The net variables represent the physical connection between structural entities such as logic gates. These variables do not store values except trireg. These variables have the value of their drivers, which changes continuously by the driving circuit. Some net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1, and trireg. A net data type must be used when a signal is: The output of some devices drives it. It is declared as an input or in-out port. On the left-hand side of a continuous assignment.  1. Wire A wire represents a physical wire in a circuit and is used to connect gates or modules. The value of a wire can be read, but not assigned to, in a function or block. A wire does not store its value but must be driven by a continuous assignment statement or by connecting it to the output of a gate or module. 2. Wand (wired-AND) The value of a wand depends on logical AND of all the drivers connected to it. 3. Wor (wired-OR) The value of wor depends on the logical OR of all the drivers connected to it. 4. Tri (three-state) All drivers connected to a tri must be z, except one that determines the tri's value. 5. Supply0 and Supply1 Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power). Registers A register is a data object that stores its value from one procedural assignment to the next. They are used only in functions and procedural blocks. An assignment statement in a procedure act as a trigger that changes the value of the data storage element. Reg is a Verilog variable type and does not necessarily imply a physical register. In multi- bit registers, data is stored as unsigned numbers, and no sign extension is done for what the user might have thought were two's complement numbers. Some register data types are reg, integer, time, and real.reg is the most frequently used type. Reg is used for describing logic. An integer is general-purpose variables. They are used mainly loops-indices, parameters, and constants. They store data as signed numbers, whereas explicitly declared reg types store them as unsigned. If they hold numbers that are not defined at compile-time, their size will default to 32-bits. If they hold constants, the synthesizer adjusts them to the minimum width needed at compilation. Real in system modules. Time and realtime for storing simulation times in test benches. Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time.  The reg variables are initialized to x at the start of the simulation. Any wire variable not connected to anything has the x value. The size of a register or wire may be specified during the declaration. When the reg or wire size is more than one bit, then register and wire are declared vectors. Verilog String Strings are stored in reg, and the width of the reg variable has to be large enough to hold the string. Each character in a string represents an ASCII value and requires 1 byte. If the variable's size is smaller than the string, then Verilog truncates the leftmost bits of the string. If the variable's size is larger than the string, then Verilog adds zeros to the left of the string. Source: https://bit.ly/3CEDirl