Impare RTL Day 2 - Intro to Verilog - PDF
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This document is an introduction to Verilog, a hardware description language (HDL). It provides an overview of basic concepts like modules, types of concurrent blocks, signal values, and operators. The document likely serves as supplementary material for computer science students learning Verilog.
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Agenda: Day Two Unit Agenda Lab 1 Modules and Blocks 2 Numbers, Data types and Operators 3 Con...
Agenda: Day Two Unit Agenda Lab 1 Modules and Blocks 2 Numbers, Data types and Operators 3 Control Constructs All rights reserved Impare @2021 Last Modified: 12/12/21 Revision: 1-7 1- 1 Verilog Overview ❖ Basic unit is a module ❖ Three types of concurrent blocks ❖ always ❖ initial ❖ assign ❖ Support for clocks, time progression,registers, and wires ❖ Supports 4 states: 0,1,x,z All rights reserved Impare @2021 Last Modified: 12/12/21 Revision: 1-7 1- 2 Signal Values and Resolution ❖ ‘0’ ❖ Zero, Low, False, Logic low, Ground, VSS, Negative Assertion ❖ ‘1’ ❖ One, High, True, Logic High, Power, VDD, VCC, Positive Assertion ❖ ‘X’ ❖ Unknown: Occurs at Logical Conflict which cannot be resolved ❖ ‘Z’ ❖ Hi-Z: High Impedance, Tristated, Disabled Driver All rights reserved Impare @2021 Last Modified: 12/12/21 Revision: 1-7 1- 3 Module ❖ Modules are basic building blocks ❖ Description of the logic being modeled is placed inside modules ❖ Module definition starts with keyword module ❖ Ends with the keyword endmodule ❖ Example: Need a better example with initial/always module hello; initial $display(“Hello World!”); endmodule All rights reserved Impare @2021 Last Modified: 12/12/21 Revision: 1-7 1- 4 Module Ports ❖ Modules communicate with the outside world through ports ❖ Module port are same as pins in hardware ❖ For Example: module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; d q always @(posedge clk) begin dff.v q
