CS1A: Intro to CS - Hardware Lecture Notes PDF

CS1A: Intro to CS Hardware Hardware ☀Input/Output (I/O) Devices ☀Secondary Storage ☀Memory...

CS1A: Intro to CS Hardware Hardware ☀Input/Output (I/O) Devices ☀Secondary Storage ☀Memory ☀Buses ☀Central Processing Unit (CPU) ☀Fetch-Decode-Execute (c) Michele Rousseau Hardware HARDWARE  Refers to the physical components of the computer Anything you can physically touch inside the box or outside Outside ◘ Mouse ◘ Keyboard ◘ Monitor Inside ◘ Motherboard ◘ Memory ◘ Hardrive (c) Michele Rousseau ◘ Etc.. Hardware 1 (c) Dr. Michele L. Rousseau 1 CS1A: Intro to CS Hardware  Inside your Computer Secondary Storage Memory (RAM) Ports Buses Buses to Input/Ouput(I/O) Devices Central Image: Public Domain Processing edit: annotations Unit Hardware 2 (c) Michele Rousseau Ports to I/O Devices Slots for ports Input/Ouput(I/O) Power Devices Supply RAM(Memory) slots CPU Hard Drive & DVD Drive Photo: © Michele Rousseau (c) Michele Rousseau Hardware 3 (c) Dr. Michele L. Rousseau 2 CS1A: Intro to CS Hardware RAM(Memory) Ports to Input/Output Devices CPU Photo: © Michele Rousseau Slots for more ports (c) Michele Rousseau Hardware I/O Devices 4 Non-storage – Input/Output (I/O) Devices  Allow the computer to communicate with the outside world - Do not store data Keyboard Monitor Printer Illustration: Public Domain Mouse Microphone Speakers Image: Public Domain Etc… Illustration: Public Domain (c) Michele Rousseau Hardware 5 (c) Dr. Michele L. Rousseau 3 CS1A: Intro to CS Hardware Input/Output (I/O) Storage Devices (AKA Auxiliary Storage Devices or Secondary Storage)  Cheaper than memory  Non-volatile Data stays on the device when the device is turned off  Current Technologies Hard Disk Drives (HDD) Solid State Drives (SDD) Hybrid Hard Drives (HHD or SSHD) SD and MicroSD cards USB Flash Drives (c) Michele Rousseau Hardware 7 Hard Disk Drives (HDD)  Magnetic Drives Invented by IBM in 1956 Constructed of light aluminum alloy OR → glass or ceramic (more resistant to heat) Coated with magnet material (ferrite compound) ◘ On both sides The drive is broken down into bit-sized blocks ◘ Determines the bit (0 or 1) by the polarization of a block Spins at 4200 RPM – 15000 RPM (typically 5400 – 7200) ◘ Uses a head to read/write Image: Public Domain Image: CC by SA 3.0 Image: CC - BlickPixel @ pixabay Eric Gaba @ wikimedia Can have several platters Typically store in the high GBs/ low TBs Come in different Sizes ◘ 3.5” for Desktops and 2.5” for laptops (c) Michele Rousseau Hardware 8 (c) Dr. Michele L. Rousseau 4 CS1A: Intro to CS Hardware Solid State Drives (SSD)  Semiconductor Storage Devices Invented in 1978 by StorageTek  Now they use NAND Flash Memory Invented in 1980 by Toshiba Special type of Electronically Erasable Programmable Read Only Memory ◘ Can Read/Write ◘ Non-Volatile ◘ Chip Technology  Were very expensive initially Image: Public Domain (c) Michele Rousseau Hardware 9 SSDs vs. HDD Pros (SSD Compared to HDD) Cons ◘ Much faster ◘ More Expensive HDD reads @ ~125MBps ◘ Less Capacity SSD reads @ ~550MBps ◘ Harder to recover ◘ More Durable data on failure ◘ Size Most about the size of a 2.5” Drive Some are smaller ◘ Quieter Image: CC by SA 4.0 ◘ Runs Cooler – so less fan usage Vladsinger @ wikimedia Image: CC by SA M. Pintor @ wikimedia  HHD – Hybrid Hard Drives Combo SSD and HDD OS and frequently used programs on SSD (c) Michele Rousseau Hardware 10 (c) Dr. Michele L. Rousseau 5 CS1A: Intro to CS Hardware Smaller Flash Ram Based Storage  Secure Digital (SD) Cards Invented in 1999 by SD-3C LLC Small, Light & Very Durable Many variations (to improve speed & Image: Public Domain Capacity)  Micro SD – AKA T-Flash, TransFlash Invented in 2005 by SanDisk for smaller devices (cell phones)  USB flash drives → AKA flash drives, USB drives, jump drives, pen drives, thumb Image: Public Domain drives, key drives, tokens Invented in 2000 by IBM More Portable than SD (c) Michele Rousseau Hardware 12 Memory  Collection of storage locations Not the same as a hard drive this is internal to the system – i.e. located on the mother board MUCH faster  Each has its own address 1 001 2 010 3 011 Like a street address – but always unique The address is in binary (1s and 0s) 4 100 5 101 6 110  Remember bytes? More useful for storing information than 1 bit Used to represent a character in ASCII ◘ American Standard Code for Information Interchange ◘ Used to be 128 chars – extended is 256 chars (c) Michele Rousseau Hardware 15 (c) Dr. Michele L. Rousseau 6 CS1A: Intro to CS Hardware 3 types of Memory  RAM Random Access Memory Image: Public Domain ◘ Read / Write ◘ ALL programs and data must be in RAM to be processed ◘ Volatile ◘ Most of main memory  ROM Read Only Memory ◘ Contents written my computer manufacturer ◘ Read only ➔ can’t write to it ◘ “Bootstrap” is on the ROM chip ◘ Non-volatile (c) Michele Rousseau Hardware 16 Types of Memory (2)  Cache Faster than RAM slower than CPU registers Between registers and primary memory Cheaper and more plentiful than registers Relatively small amount of memory ◘ Compared to RAM Contains a copy of a portion of main memory ◘ CPU - checks to see if requested portion is in cache ◘ If so, it retrieves it ◘ If not, it has to go to main → replaces cache with new data retrieved ◘ Most processing is performed with a small portion of data → so mostly will be in cache (c) Michele Rousseau Hardware 17 (c) Dr. Michele L. Rousseau 7 CS1A: Intro to CS Hardware How Do We Measure Storage? We measure memory & external storage in terms of bytes Number of Decimal Unit Bytes Approximation kilobyte 210 103 megabyte 220 106 gigabyte 230 109 terabyte 240 1012 petabyte 250 1015 exabyte 260 1018 zetta 270 1021 yotta 280 1024 (c) Michele Rousseau Hardware 18 Buses – Electronic Pathways Image: Public Domain Image: Public Domain Image: Public Domain Image: Public Domain (c) Michele Rousseau Hardware 19 (c) Dr. Michele L. Rousseau 8 CS1A: Intro to CS Hardware BUSES  Electrical pathways (wires)  These connect all the components to the CPU  System Bus Internal Bus CPU and Memory  Expansion Bus External Bus CPU and I/O Devices Image: Public Domain (c) Michele Rousseau Hardware 20 Bit Transmission Each bus transmits 1 bit of information per wire  If we have an 8-bit bus, that means we have 8 wires. We can transmit 8-bits at a time.  With a 16-bit bus, then we have 16 wires and transmit twice as much information. (c) Michele Rousseau 21 Hardware (c) Dr. Michele L. Rousseau 9 CS1A: Intro to CS Hardware The System Bus  The CPU the address, data, and instructions to/from main Memory via the system bus Von Neumann’s paper proposed a single bus, but this created a bottleneck so…  3 types of Buses Data Bus → moves data between main memory & the CPU registers Address Bus → carries the address of the data that the data bus is accessing Control Bus → carries the instructions that specify read or write commands (c) Michele Rousseau Hardware 23 System Buses  The CPU transfers data, addresses and instructions to/from main Memory via the system bus Von Neumann’s paper proposed a single bus, but this created a bottleneck so…  3 types of Buses Data Bus → moves data between main memory and the CPU registers Address Bus → holds the address of the data that the data bus is accessing Control Bus → carries the instructions that specify how the information transfer is to take place (c) Michele Rousseau Hardware 24 (c) Dr. Michele L. Rousseau 10 CS1A: Intro to CS Hardware System/Internal Bus  Data Bus → moves data from the main memory to the CPU and back ◘ 16 bit → 16 wires ◘ 32 bit → 32 wires… etc 1 word is transmitted at a time  Address Bus → holds the address of the data that the data bus is currently accessing Used to access a specific word in memory # of wires is determines the # of addressable locations ◘ If we have 3 wires there are 23 or 8 addresses ◘ Because… with 3 bits we can have 8 unique combinations of 0’s and 1’s - in other words ➔ 8 unique addresses Typically the word size ◘ (rarely a multiple or fraction thereof)  Control Bus → Indicates whether or not a read or write is to be performed (c) Michele Rousseau Hardware 26 Sending Data to Memory An ADDRESS is sent indicating which address to send data to in memory. Address Bus RAM (Memory) The write INSTRUCTION is sent. Michele’s WRITE Control Bus CPU Data Bus Finally, the data is sent to the appropriate address in memory. (c) Michele Rousseau Hardware 29 (c) Dr. Michele L. Rousseau 11 CS1A: Intro to CS Hardware Reading Data from Memory An ADDRESS is sent indicating which address to read data from in memory. Address Bus RAM (Memory) The read INSTRUCTION is sent. Michele’s Control Bus CPU READ Data Bus Finally, the data is sent to the CPU. Note: Data flow is uni-directional for the Address & Control Buses, but bi-directional for the Data Bus (c) Michele Rousseau Hardware 30 Expansion Bus → I/O devices communicate with the CPU/Memory through ports → These ports are connected to an Expansion or PCI bus → The Expansion or PCI bus communicates with the System Bus through a bridge → The bridge manages traffic between the Expansion bus and the System bus → The system bus is much faster than the Expansion or PCI bus (c) Michele Rousseau Hardware 31 (c) Dr. Michele L. Rousseau 12 CS1A: Intro to CS Hardware Word Size Word Size ➔ The amount of data that can be handled as a unit at one time CPU Registers ➔ Storage internal to the CPU (More on this later) Generally speaking… Word Size = Register Size = Data Bus Size = Address Bus Size When we say we have a x-bit system we are referencing the word size 32-bit system 64-bit system and so on The word size then also dictates the maximum RAM a system can support as it indicates the maximum # of addressable locations Remember each byte has to addressed ◘ 8-bit system: Max. RAM = 28 or 256 total address = 256 Bytes of ram ◘ 16-bit system: Max. RAM = 216 or 65,536 total address = 65 KB of ram ◘ 32-bit system: Max. RAM = 232 or 4.3 billion total address = 4 GB of ram  This is one of many factors that impact system speed (c) Michele Rousseau Hardware 32 The CPU interacts with Memory SYSTEM BUS (c) Michele Rousseau Hardware 33 (c) Dr. Michele L. Rousseau 13 CS1A: Intro to CS Hardware Mauchly & Eckert  Built the ENIAC & UNIVAC … while building the ENIAC Came up with a way to store programs To create a new program on the ENIAC wires had to be unplugged and plugged into new sockets Image: Public Domain  John Von Neumann published the idea of storing programs and data internally  We call this the Von Neumann architecture (c) Michele Rousseau Hardware 34 The CPU  Central Processing Unit The “brain” of the computer Image: © Michele Rousseau Divided into 3 parts (Registers, CU, ALU) CPU Registers PC Program Counter Control Unit } (CU) R1 Data R2 R3 Arithmetic Logic IR Unit (ALU) Image: © Michele (c) Michele Rousseau Hardware Rousseau 35 (c) Dr. Michele L. Rousseau 14 CS1A: Intro to CS Hardware Elements of the CPU Control Unit (CU) Transfers data to and from memory Calls the Arithmetic Logic Unit when necessary Fetches instructions Interprets instructions Executes instructions in order Arithmetic Logic Unit (ALU) Performs all arithmetic & logical operations Arithmetic operations ◘ Increment & Decrement (unary operations – 1 input/operand) ◘ Addition & Subtraction(binary operations – 2 inputs/operands) ◘ Multiplication & Division Logical operations ◘ NOT, AND, OR, and XOR (c) Michele Rousseau Hardware 36 Registers Registers are very fast temporary locations used to store data on the CPU Data to be processed is not in memory ◘ it is moved to the CPU (registers) Extremely fast - speeds execution time Registers hold partial results of calculations before they can be stored back into memory Two basic types of registers ◘General purpose (for data and partial calculations) ◘Special purpose registers (c) Michele Rousseau Hardware 37 (c) Dr. Michele L. Rousseau 15 CS1A: Intro to CS Hardware Special Purpose Registers The CPU contains a number of Special Purpose Registers Two Basic Special Purpose Registers  Program Counter (PC) Contains the address location of the next instruction to be executed Once a statement is interpreted the PC is updated ◘ gets the memory address of the next instruction  Instruction Register (IR) Contains the current instruction being processed (c) Michele Rousseau Hardware 39 Executing Programs  To execute a program, it must first be copied from the hard drive into RAM The operating system (OS) handles this ◘ double click an executable file LDA 1000 LDA 1000 ADD 1001 ADD 1001 STO 1002 STO 1002 (c) Michele Rousseau Hardware 40 (c) Dr. Michele L. Rousseau 16 CS1A: Intro to CS Hardware Von-Neumann Architecture  The Von-Neumann architecture stores both the program and data into main memory MAIN MEMORY CONTENTS ADDRESS } 500 LDA 1000 501 ADD 1001 Program 502 STO 1002 … …. } 1000 03 1001 04 Data 1002 05 Image: © Michele Rousseau (c) Michele Rousseau Hardware 41 The CPU interacts with Memory … through the control unit CPU Registers PC } CU SYS. BUS R1 MAIN MEMORY Data R2 (RAM) R3 ALU IR Image: © Michele Rousseau (c) Michele Rousseau Hardware 42 (c) Dr. Michele L. Rousseau 17 CS1A: Intro to CS Hardware Fetch-Decode-Execute Cycle  Once the program & data are in Main Memory the instructions are executed by the CPU using the FETCH-DECODE-EXECUTE CYCLE These are the basic steps the CPU carries our to process a single instruction 1. The Control unit fetches the next instruction from main memory It uses the program counter (PC) to determine where the next instruction is located Places the instruction in the instruction register (IR) 2. The instruction is decoded or interpreted Any data required to execute the instruction are fetched from memory by the CU and placed into registers The program counter is incremented to the address of the next instruction 3. The ALU executes the instructions and places the results in registers (c) Michele Rousseau Hardware 43 Fetch - Decode - Execute  The Program Counter (PC) contains the address of the next instruction that is to be fetched-decoded- executed. This will increment automatically as the current instruction is being decoded. MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 500 501 ADD 1001 CU BUS } R1 502 STO 1002 Data R2 … …. R3 1000 03 ALU IR 1001 04 1002 05 (c) Michele Rousseau Hardware 44 (c) Dr. Michele L. Rousseau 18 CS1A: Intro to CS Hardware Fetch  The Control Unit (CU) fetches the instruction from main memory and store it in the Instruction Register (IR). MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 500 501 ADD 1001 CU BUS } R1 502 STO 1002 Data R2 … …. R3 1000 03 ALU IR LDA 1000 1001 04 1002 05 (c) Michele Rousseau Hardware 45 Decode  The Control Unit (CU) decodes the instruction in the Instruction Register (IR) and fetches any necessary data which is put in a data register.  Then the Program Counter (PC) is updated to the address of the next instruction. MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 501 500 501 ADD 1001 CU BUS } R1 502 STO 1002 Data R2 … …. R3 1000 03 ALU IR LDA 1000 1001 04 1002 05 (c) Michele Rousseau Hardware 46 (c) Dr. Michele L. Rousseau 19 CS1A: Intro to CS Hardware Execute  The Control Unit (CU) executes the decoded instruction. ➔ LDA 1000 means to load what is in the address 1000 into a register (R1) MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 501 501 ADD 1001 CU BUS } R1 03 502 STO 1002 Data R2 … …. R3 1000 03 ALU IR LDA 1000 1001 04 1002 05 (c) Michele Rousseau Hardware 47  That is one iteration of Fetch-Decode Execute  Now for the next instruction (c) Michele Rousseau Hardware 48 (c) Dr. Michele L. Rousseau 20 CS1A: Intro to CS Hardware Fetch  The Control Unit(CU) fetches the instruction from main memory and stores it in the instruction register (IR). MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 501 501 ADD 1001 CU BUS } R1 03 502 STO 1002 Data R2 … …. R3 1000 03 ALU IR ADD 1001 1001 04 1002 05 (c) Michele Rousseau Hardware 49 Decode  The Control Unit (CU) decodes the instruction in the Instruction Register (IR) and fetches any necessary data which is put in a data register (R2). (ADD 1001 ➔ add the contents of 1001)  Then the Program Counter (PC) is updated to the address of the next instruction. MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 501 502 501 ADD 1001 CU BUS } R1 03 502 STO 1002 Data R2 04 … …. R3 1000 03 ALU IR ADD 1001 1001 04 1002 05 (c) Michele Rousseau Hardware 50 (c) Dr. Michele L. Rousseau 21 CS1A: Intro to CS Hardware Execute  The Control Unit (CU) executes the instruction by calling upon the Arithmetic Logic Unit (ALU) to perform the addition (ADD 1001 means to add the data in address 1001 which is now in register 2 (R2)  The result gets stored in another register (R3) MAIN CONTENTS MEMORY CPU ADDRESS Registers 500 LDA 1000 PC 502 501 ADD 1001 CU BUS } R1 03 502 STO 1002 Data R2 04 … …. R3 07 1000 03 ALU IR ADD 1001 1001 04 1002 05 (c) Michele Rousseau Hardware 51 Fetch-Decode-Execute  The Fetch-Decode-Execute cycle continues until all instructions are executed  Bear in mind that modern processors can execute billions of instructions per second  Modern processors also have more general purpose and special purpose registers  This is a basic overview of how a simple processor works. Modern computers have several processors working in parallel. (c) Michele Rousseau Hardware 52 (c) Dr. Michele L. Rousseau 22