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CSC-25 High Performance Architectures Lecture Notes – Chapter IX-B Buses Denis Loubach [email protected] Department of Computer Systems Computer Science Division – IEC Aeronautics Institute of Technology – IT...
CSC-25 High Performance Architectures Lecture Notes – Chapter IX-B Buses Denis Loubach [email protected] Department of Computer Systems Computer Science Division – IEC Aeronautics Institute of Technology – ITA 1st semester, 2024 Detailed Contents Buses Bus Width Overview Bus Clocking Scheme Definitions Operation Pros & Cons Arbitration Method Bus Design Examples Overview References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 2/23 Outline Buses Bus Design Examples References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 3/23 Buses Overview Transfer rates in I/O devices can range from 0.0001 Mbps e.g., keyboard, to 800 ∼ 8,000 Mbps e.g., graphics display System, i.e., memory and I/O, bus simplified view 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 4/23 Buses (cont.) Definitions Bus – shared communication link to carry address, data and control signals I set of wires used to connect multiple subsystems I basic tool for putting together large and complex systems 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 5/23 Buses (cont.) Definitions Address bus (address lines) I identifies source of a data flow I bandwidth gives the maximum addressing capacity Data bus (data lines) I carries data or instructions, i.e., does not matter on that level I typically bidirectional I bandwidth determinant for performance Control bus (control lines) I read/write I interruptions I clock 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 6/23 Buses (cont.) Pros & Cons Versatility I new devices can be easily integrated to the system I peripherals can be moved around different computers with same bus standard Low cost I single set of wires shared in different ways 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 7/23 Buses (cont.) Pros & Cons Communication bottleneck I bus bandwidth can limit the maximum I/O throughput Maximum bus speed largely limited by I bus length and number of devices on the bus I need to support a range of devices with widely differences in I latencies I data transfer rates 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 8/23 Outline Buses Bus Design Examples References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 9/23 Bus Design Overview Both bus speed and bandwidth are greatly impacted by four main points 1. bus width 2. bus clocking scheme 3. operation 4. arbitration method 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 10/23 Bus Design (cont.) Bus Width Generally, the number of address lines determines the size of the addressable memory The greater the number of lines, more wires and larger connectors, i.e., the hardware becomes more expensive I 8088: 20 address lines; 80286: + 4 lines; 80386: + 8 lines The trend to increase bus width to increase bus capacity creates physical connection problems Designers often make multiplexing of data and addresses in different phases/time to reduce the number of lines I but this also reduces the performance of the bus 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 11/23 Bus Design (cont.) Bus Clocking Scheme Synchronous bus Asynchronous bus I includes a clock in the control lines I not clocked I fixed protocol for communication, wrt the I can accommodate a wide devices’ range clock I can be lengthened w/o caring about clock I advantage skew I involves very little logic and can run fast I requires a handshake protocol I disadvantage I all devices on the bus must run at the same clock rate I to avoid clock skew, buses cannot be long if they are fast 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 12/23 Bus Design (cont.) Operation Master versus Slave Two-parts bus transaction 1. request – issue a command and address 2. action – transferring the data Master, starts the bus transaction I issues the requests Slave, respond to the master I sends and receives data, accordingly 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 13/23 Bus Design (cont.) Operation - Obtaining access to the bus How is the bus reserved by a device that want to use it? Chaos is avoided by using master-slave scheme I only the bus master controls the access to the bus, it starts and handles all bus requests I slave responds to r/w requests The simplest system I processor is the only bus master I all bus requests must be controlled by the processor I big drawback, i.e., processor is involved in everything 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 14/23 Bus Design (cont.) Arbitration Method Arbitration – multiple bus masters With multiple bus masters it is needed to define means of assuring that only one device will be selected as master at a time A method must consider I priority among devices I fairness, i.e., even the lowest priority device must operate 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 15/23 Bus Design (cont.) Arbitration Method Four possible arbitration classes 1. distributed arbitration by self-selection, i.e., each device that waits for the bus places its own code, i.e., indicating its identity 2. distributed arbitration by collision detection, e.g., Ethernet 3. authorization given in sequence, i.e., daisy chain 4. authorization given centrally, i.e., centralized arbitration 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 16/23 Bus Design (cont.) Arbitration Method - Daisy Chain Simple But, cannot assure fairness I a low-priority device may be locked out forever The use of daisy chain “grant” signal also impacts bus speed 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 17/23 Bus Design (cont.) Arbitration Method - Centralized Arbitration with a Bus Arbiter 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 18/23 Outline Buses Bus Design Examples References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 19/23 Examples Peripheral Component Interconnect - PCI Express (PCI-e) I created by Intell, Dell, HP, IBM I connects HDD, SSD, Ethernet, graphics, and other cards in personal computers I point-to-point topology, considering separate serial links connecting all devices I replaces other standards, e.g., Accelerated Graphics Port - AGP, PCI, PCI-eXtended InfiniBand - IB I originated by Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft, and Sun I typically used in clusters/racks I very high throughput and very low latency 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 20/23 Examples (cont.) MIL-STD-1553 I avionic data bus for use with military avionics I also used in spacecrafts, dual technology I bus controller handling multiple remote terminals connected with redundant links ARINC1 429 I predominant avionics data bus I used on most commercial aircraft I pair of wires accommodates one transmitter and up to 20 receivers Avionics Full-Duplex Switched Ethernet - AFDX I implementation of deterministic Ethernet, defined by ARINC I addresses real-time issues 1 Aeronautical Radio INC 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 21/23 Outline Buses Bus Design Examples References 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 22/23 Information to the reader Lecture notes mainly based on the following references Castro, Paulo André. Notas de Aula da disciplina CES-25 Arquiteturas para Alto Desempenho. ITA. 2018. Hennessy, J. L. and D. A. Patterson. Computer Architecture: A Quantitative Approach. 6th. Morgan Kaufmann, 2017. Patterson, D. and S. Kong. Lecture notes, CS152 Computer Architecture and Engineering, Lecture 19: I/O Systems. Online. 1995. –.Lecture notes, CS152 Computer Architecture and Engineering, Lecture 20: Busses and OS’s Responsibilities. Online. 1995. 1st semester, 2024 Loubach CSC-25 High Performance Architectures ITA 23/23