ITSU1001 Introduction to Computer Systems and Networking Lesson 6 PDF

ITSU1001 INTRODUCTION TO COMPUTER SYSTEMS AND NETWORKING LESSON 6: Buses, Registers and CPU Instructions Copyright © 2023 VIT, All rights reserved  Bus ITSU1001...

ITSU1001 INTRODUCTION TO COMPUTER SYSTEMS AND NETWORKING LESSON 6: Buses, Registers and CPU Instructions Copyright © 2023 VIT, All rights reserved  Bus ITSU1001 Lesson 6 The physical connection that makes it possible to transfer data from one location in the computer system to another Group of electrical or optical conductors for carrying signals from one location to another Wires or conductors printed on a circuit board Line: each conductor in the bus 4 kinds of signals 1. Data 2. Addressing 3. Control signals 4. Power (sometimes) Copyright © 2021 VIT, All rights reserved 2 Copyright © 2023 VIT, All rights reserved  Bus Characteristics ITSU1001 Lesson 6 Number of separate conductors Data width in bits carried simultaneously Addressing capacity Lines on the bus are for a single type of signal or shared Throughput - data transfer rate in bits per second Distance between two endpoints Number and type of attachments supported Type of control required Defined purpose Features and capabilities Copyright © 2021 VIT, All rights reserved 3 Copyright © 2023 VIT, All rights reserved  Bus Categorizations ITSU1001 Lesson 6 Parallel vs. serial buses Direction of transmission Simplex – unidirectional Half duplex – bidirectional, one direction at a time Full duplex – bidirectional simultaneously Method of interconnection Point-to-point – single source to single destination Cables – point-to-point buses that connect to an external device Multipoint bus – also broadcast bus or multidrop bus Connect multiple points to one another Copyright © 2021 VIT, All rights reserved 4 Copyright © 2023 VIT, All rights reserved  Parallel vs. Serial Buses ITSU1001 Lesson 6 Parallel High throughput because all bits of a word are transmitted simultaneously Expensive and require a lot of space Subject to radio-generated electrical interference which limits their speed and length Generally used for short distances such as CPU buses and on computer motherboards Serial 1 bit transmitted at a timed Single data line pair and a few control lines For many applications, throughput is higher than for parallel because of the lack of electrical interference Copyright © 2021 VIT, All rights reserved 5 Copyright © 2023 VIT, All rights reserved  Point-to-point vs. Multipoint ITSU1001 Lesson 6 Plug-in device Broadcast bus Example: Ethernet Shared among multiple devices Copyright © 2021 VIT, All rights reserved 6 Copyright © 2023 VIT, All rights reserved  Classification of Instructions ITSU1001 Lesson 6 Data Movement (load, store) Most common, greatest flexibility Involve memory and registers What’s this size of a word ? 16? 32? 64 bits? Arithmetic Operators + - / * ^ Integers and floating point Boolean Logic Often includes at least AND, XOR, and NOT Single operand manipulation instructions Negating, decrementing, incrementing, set to 0 Copyright © 2021 VIT, All rights reserved 7 Copyright © 2023 VIT, All rights reserved  More Instruction Classifications ITSU1001 Lesson 6 Bit manipulation instructions Flags to test for conditions Shift and rotate Program control Stack instructions Multiple data instructions I/O and machine control Copyright © 2021 VIT, All rights reserved 8 Copyright © 2023 VIT, All rights reserved  Register Shifts and Rotates ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 9 Copyright © 2023 VIT, All rights reserved  Program Control Instructions ITSU1001 Lesson 6 Program control Jump and branch Subroutine call and return Operation of CALL and RETURN Instructions Copyright © 2021 VIT, All rights reserved 10 Copyright © 2023 VIT, All rights reserved  Stack Instructions ITSU1001 Lesson 6 Stack instructions LIFO method for organizing information Items removed in the reverse order from that in which they are added Push Pop Copyright © 2021 VIT, All rights reserved 11 Copyright © 2023 VIT, All rights reserved  Fixed Location Subroutine Return Address Storage ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 12 Copyright © 2023 VIT, All rights reserved  Stack Subroutine Return Address Storage ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 13 Copyright © 2023 VIT, All rights reserved  Block of Memory as a Stack ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 14 Copyright © 2023 VIT, All rights reserved  Multiple Data Instructions ITSU1001 Lesson 6 Perform a single operation on multiple pieces of data simultaneously SIMD: Single Instruction, Multiple Data Commonly used in multimedia, vector and array processing applications Operation of a 4-Wide SIMD ADD Instruction Copyright © 2021 VIT, All rights reserved 15 Copyright © 2023 VIT, All rights reserved Instruction Elements ITSU1001 Lesson 6 OPCODE: task Source OPERAND(s) Result OPERAND Location of data (register, memory) Addresses Explicit: included in instruction Implicit: default assumed Source Result OPCODE OPERAND OPERAND Copyright © 2021 VIT, All rights reserved 16 Copyright © 2023 VIT, All rights reserved  Instruction Format ITSU1001 Lesson 6 Simple 32-bit Instruction Format Machine-specific template that specifies – Length of the op code – Number of operands – Length of operands Typical two operation register Move format Copyright © 2021 VIT, All rights reserved 17 Copyright © 2023 VIT, All rights reserved  Instructions ITSU1001 Lesson 6 Instruction Direction given to a computer Causes electrical or optical signals to be sent through specific circuits for processing Instruction set Design defines functions performed by the processor Differentiates computer architecture by the Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes) Copyright © 2021 VIT, All rights reserved 18 Copyright © 2023 VIT, All rights reserved  Instruction Word Size ITSU1001 Lesson 6 Fixed vs. variable size Pipelining has mostly eliminated variable instruction size architectures Most current architectures use 32-bit or 64-bit words Addressing Modes Direct Mode used by the LMC Register Deferred Also immediate, indirect, indexed Copyright © 2021 VIT, All rights reserved 19 Copyright © 2023 VIT, All rights reserved  Deferred Register Addressing ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 20 Copyright © 2023 VIT, All rights reserved  Instruction Format Examples ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 21 Copyright © 2023 VIT, All rights reserved  Instruction Format Examples ITSU1001 Lesson 6 Copyright © 2021 VIT, All rights reserved 22 Copyright © 2023 VIT, All rights reserved