Computer Architecture Unit 1 PDF

**[UNIT-1]** **[Functional units of digital system]** The internal architectural design of computers differs from one system model to another. However, the basic organization remains the same for all computer systems. The following five units (also called ***"The functional units"***) correspond t...

**[UNIT-1]** **[Functional units of digital system]** The internal architectural design of computers differs from one system model to another. However, the basic organization remains the same for all computer systems. The following five units (also called ***"The functional units"***) correspond to the five basic operations performed by all computer systems. C:\\Users\\ty\\Desktop\\functional-units-of-digital-system.png **Input Unit** - - **   **In short, an input unit performs the following functions. 1. 2. 3. **Output Unit** An output unit is just the reverse of that of an input unit. It supplied information and results of computation to the outside world. Thus it links the computer with the external environment. As computers work with binary code, the results produced are also in the binary form. Hence, before supplying the results to the outside world, it must be converted to human acceptable (readable) form. This task is accomplished by units called output interfaces. In short, the following functions are performed by an output unit. 1. 2. 3. **Storage Unit** - - In short, the specific functions of the storage unit are to store: 1. 2. 3. **                     ** **Central Processing Unit (CPU)** - - The control Unit and the Arithmetic and Logic unit of a computer system are jointly known as the Central Processing Unit (CPU). The CPU is the brain of any computer system. In a human body, all major decisions are taken by the brain and the other parts of the body function as directed by the brain. Similarly, in a computer system, all major calculations and comparisons are made inside the CPU and the CPU is also responsible for activating and controlling the operations of other units of a computer system. **Arithmetic and Logic Unit (ALU)** - - - - - **Control Unit** How the input device knows that it is time for it to feed data into the storage unit? How does the ALU know what should be done with the data once it is received? And how is it that only the final results are sent to the output devices and not the intermediate results? All this is possible because of the control unit of the computer system. By selecting, interpreting, and seeing to the execution of the program instructions, the control unit is able to maintain order and directs the operation of the entire system. - **[BUSES]** Definition - What does Bus mean? -------------------------------- A bus is a subsystem that is used to connect computer components and transfer data between them. For example, an internal bus connects computer internals to the motherboard.\ \ A bus may be parallel or serial. Parallel buses transmit data across multiple wires. Serial buses transmit data in bit-serial format.  Control Bus ----------- The motherboard\'s control bus manages the activity in the system. The control bus, like the other buses, is simply a set of connections among the parts in the computer. All parts \"agree to recognize\" that if one connection carries a voltage and the next one does not, it means that the central processor reads from memory. If the connections reverse roles, the processor writes to memory. Other connections deal with the \"chunking\" of data 8, 16, 32 or 64 bits at a time. Still others determine if data is being shuttled to the central processor from memory or the keyboard. This signaling system prevents data from going to the wrong place. Data Bus -------- The data bus acts as a conduit for data from the keyboard, memory and other devices. It passes information at speeds up to billions of characters per second. The central processor reads the data, performs calculations, and moves new data back to memory, the hard drive and other locations. The control bus determines which direction the data is moving. Address Bus ----------- The computer must be able to access every character of memory rapidly, so every character has its own address number. The central processor specifies which addresses it wants to read or write and the address bus carries this information to a memory controller circuit, which locates and fetches the information. Some locations, called random-access memory, hold program instructions and temporary calculation results. Other locations point to the hard drive, mouse and keyboard. The control bus specifies which of these two sets of addresses become active for a particular memory operation. Bus and Memory Transfers ======================== A digital system composed of many registers, and paths must be provided to transfer information from one register to another. The number of wires connecting all of the registers will be excessive if separate lines are used between each register and all other registers in the system. A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-register configuration system. A bus consists of a set of common lines, one for each bit of register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during a particular register transfer. The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4 \* 1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2). We have used labels to make it more convenient for you to understand the input-output configuration of a Bus system for four registers. For instance, output 1 of register A is connected to input 0 of MUX1. C:\\Users\\ty\\Desktop\\Mux image.png The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The selection lines choose the four bits of one register and transfer them into the four-line common bus. When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data inputs of the multiplexers. Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by register B. The following function table shows the register that is selected by the bus for each of the four possible binary values of the Selection lines.  **[Three-State Bus Buffers]** A bus system can also be constructed using **three-state gates** instead of multiplexers. The **three state gates** can be considered as a digital circuit that has three gates, two of which are signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance state. The most commonly used three state gates in case of the bus system is a **buffer gate**. The graphical symbol of a three-state buffer gate can be represented as: C:\\Users\\ty\\Desktop\\graphic symbal.png The following diagram demonstrates the construction of a bus system with three-state buffers.  - - - - Memory Transfer --------------- Most of the standard notations used for specifying operations on memory transfer are stated below. - - - - - - 1. - - 1. - What is Bus Arbitration? ------------------------ - - - - **Types of Bus Arbitration** There are two types of bus arbitration namely 1. 2. Only single bus arbiter performs the required arbitration and it can be either a processor or a separate DMS controller. There are three arbitration schemes which run on centralized arbitration. - - - - **Advantages --** - - **Disadvantages --** - - - **(ii) [Polling method --]**\ In this method, the devices are assigned unique priorities and complete to access the bus, but the priorities are dynamically changed to give every device an opportunity to access the bus.  In this the controller is used to generate the addresses for the master. Number of address line required depends on the number of master connected in the system.  For example, if there are 8 masters connected in the system, at least three address lines are required.  In response to the bus request controller generates a sequence of master address. When the requesting master recognizes its address, it activated the busy line ad begins to use the bus. C:\\Users\\ty\\Desktop\\polling.png **Advantages --** - - - **Disadvantages --** - **(iii) [Independent Request method] --**In this method, the bus control passes from one device to another only through the centralized bus arbiter.  In this scheme each master has a separate pair of bus request and bus grant lines and each pair has a priority assigned to it.  The built in priority decoder within the controller selects the highest priority request and asserts the corresponding bus grant signal. **Advantages --** - **Disadvantages --** - Distributed Arbitration ----------------------- - - - - - - **Register** are used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU, **[Types of Registers :]** **Memory Address Register (MAR):** This register holds the memory addresses of data and instructions. This register is used to access data and instructions from memory during the execution phase of an instruction. **Memory Data Register (MDR):**MDR which contains the data to be written into or readout of the addressed location. **Accumulator Register**: It hold the respond of operand of instruction. **Data Register:** Temporary register as MDR. **Instruction Register**: It having instruction address. **Instruction Buffer Register**:Temporary register as IR. **Program Counter** : It hold the address of instruction. **Index Register :** It is a circuit that receive ,store & output instruction changing code in a computer. **[Processor Organization]** - - - - - - - - - **[To perform a memory fetch operation]** - - - As an example, assume that the address of the memory location to be accessed is kept in register R2 and that the memory contents to be loaded into register R1. This is done by the following sequence of operations: 1\. MAR \[R2\] 2\. Read 3\. Wait for MFC signal 4\. R1 \[MDR\] **[Storing a word into memory]** The procedure of writing a word into memory location is similar to that for reading one from memory. The only difference is that the data word to be written is first loaded into the MDR, the write command is issued. As an example, assumes that the data word to be stored in the memory is in register R1 and that the memory address is in register R2. The memory write operation requires the following sequence: 1\. MAR \[R2\] 2\. MDR \[R1\] 3\. Write 4\. Wait for MFC **[Register Transfer Operation]** Register transfer operations enable data transfer between various blocks connected to the common bus of CPU. We have several registers inside CPU and it is needed to transfer information from one register another. As for example during memory write operation data from appropriate register must be moved to MDR. Since the input output lines of all the register are connected to the common internal bus, we need appropriate input output gating. The input and output gates for register Ri are controlled by the signal Ri in and Ri out respectively.Thus, when Ri in set to 1 the data available in the common bus is loaded into Ri. Similarly when, Ri out is set to 1, the contents of the register Ri are placed on the bus. To transfer data from one register to other register, we need to generate the appropriate register gating signal For example, to transfer the contents of register R1 to register R2, the following actions are needed: lEnable the output gate of register R1 by setting R1out to 1. \-- This places the contents of R1 on the CPU bus. lEnable the input gate of register R2 by setting R2 in to 1. \-- This loads data from the CPU bus into the register R2. Performing the arithmetic or logic operation: l Generally ALU is used inside CPU to perform arithmetic and logic operation. ALU is a combinational logic circuit which does not have any internal storage. Therefore, to perform any arithmetic or logic operation (say binary operation) both the input should be made available at the two inputs of the ALU simultaneously. Once both the inputs are available then appropriate signal is generated to perform the required operation. We may have to use temporary storage (register) to carry out the operation in ALU. The sequence of operations that have to carried out to perform one ALU operation depends on the organization of the CPU. Consider an organization in which one of the operand of ALU is stored in some temporary register Y and other operand is directly taken from CPU internal bus. The result of the ALU operation is stored in another temporary register Z Therefore, the sequence of operations to add the contents of register R1 to register R2 and store the result in register R3 should be as follows: 1\. R1out, Yin 2\. R2out, Add, Zin 3\. Zout, R3in **General Register organization** - - C:\\Users\\ty\\Desktop\\register org.png **EXAMPLE:**    To perform the operation R3 ← R1+R2  We have to provide following binary selection variable to the select inputs. 1.      SEL A :  001 -To place the contents of R1 into bus A. 2.      SEL B :  010 - to place the contents of R2 into bus B 3.      SEL OPR :  00010  -- to perform the arithmetic addition A+B 4.      SEL REG or SEL D :  011  -- to place the result available on output bus in R3. **CONTROL WORD** -   It consist of four fields SELA, SELB,and SELD or SELREG contains three bit each and SELOPR field contains five bits thus the total bits in the control word are 14-bits. **Encoding of register selection fields** **Binary** **Code SELA SELB SELD** **000 Input Input None** **001 R1 R1 R1** **010 R2 R2 R2** **011 R3 R3 R3** **100 R4 R4 R4** **101 R5 R5 R5** **110 R6 R6 R6** **111 R7 R7 R7** **Encoding of ALU operations** **MICROOPERATION** **SEL A** **SEL B** **SEL D OR SELREG** **SELOPR** **CONTROL WORD** -------------------- ----------- ----------- --------------------- ------------ ------------------ --------- --------- ----------- **R2 = R1+R3** **R1** **R3** **R2** **ADD** **001** **011** **010** **00010** **Stack Organization** - -  - - C:\\Users\\sony\\Desktop\\csa-stack-16-728.jpg - The element C is at the top of the stack and the stack pointer holds the address of C that is 3. The top element is popped from the stack through reading memory word at address 3 and decrementing the stack pointer by 1. Then, B is at the top of the stack and the SP holds the address of B that is 2. It can insert a new word, the stack is pushed by incrementing the stack pointer by 1 and inserting a word in that incremented location.  - - - - - - - - - - - C:\\Users\\student\\Desktop\\cpu8.png - - - - - - - - **Addressing Modes:** The most common addressing techniques are: m **Immediate** m **Direct** m **Indirect** m **Register** m **Register Indirect** m **Displacement** To explain the addressing modes, we use the following notation: **A** = contents of an address field in the instruction that refers to a memory **R** = contents of an address field in the instruction that refers to a register **EA** = actual (effective) address of the location containing the referenced operand **(X)** = contents of location X **Immediate Addressing:** The simplest form of addressing is immediate addressing, in which the operand is actually present in the instruction: OPERAND = A This mode can be used to define and use constants or set initial values of variables.  **Direct Addressing:** A very simple form of addressing is direct addressing, in which the address field contains the effective address of the operand: EA = A It requires only one memory reference and no special calculation. **Indirect Addressing:** With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. One solution is to have the address field refer to the address of a word in memory, which in turn contains a full-length address of the operand. This is know as indirect addressing: EA = (A)  **Register Addressing:** Register addressing is similar to direct addressing. The only difference is that the address field referes to a register rather than a main memory address: EA = R The advantages of register addressing are that only a small address field is needed in the instruction and no memory reference is required. The disadvantage of register addressing is that the address space is very limited. **Register Indirect Addressing:** Register indirect addressing is similar to indirect addressing, except that the address field refers to a register instead of a memory location. It requires only one memory reference and no special calculation. EA = (R) Register indirect addressing uses one less memory reference than indirect addressing. Because, the first information is available in a register which is nothing but a memory address. From that memory location, we use to get the data or information. In general, register access is much more faster than the memory access.  **Diaplacement Addressing:** A very powerful mode of addressing combines the capabilities of direct addressing and register indirect addressing, which is broadly categorized as displacement addressing: EA = A + (R) Three of the most common use of displacement addressing are: L Relative addressing l Base-register addressing l Indexing **Relative Addressing:** For relative addressing, the implicitly referenced register is the *program counter* (PC). That is, the current instruction address is added to the address field to produce the EA. Thus, the effective address is a displacement relative to the address of the instruction. **Base-Register Addressing:** A register to hold the base address of a segment, and the instruction must reference it explicitly. **Indexing:** The address field references a main memory address, and the reference register contains a positive displacement from that address.