COA Lab Manual - AIML PDF

KIET GROUP OF INSTITUTIONS, Ghaziabad Department of Computer Science & Engineering (AIML) (An ISO – 9001: 2015 Certified & ‘A+’ Grade accredited Institution by NAAC) Computer Organization and Architecture Lab (BCS352)...

KIET GROUP OF INSTITUTIONS, Ghaziabad Department of Computer Science & Engineering (AIML) (An ISO – 9001: 2015 Certified & ‘A+’ Grade accredited Institution by NAAC) Computer Organization and Architecture Lab (BCS352) Lab Manual Experiment Number < 1 > 1 Aim / Objective / Study and verify the outputs of the logic gates (AND, OR, NOT, NAND, NOR, Ex-OR, and problem Ex-NOR). statement sample Input for all gates: A=0, B=1 input expected Suppose the output of all gates dented by symbol X, then output Output of NOT Gate: X=1 {for input A} Output of AND Gate: X=0 Output of OR Gate: X=1 Output of NAND Gate: X=1 Output of NOR Gate: X=0 Output of XOR Gate: X=1 Output of XNOR Gate: X=0 2 Theory AND Gate: A multi-input circuit in which the output is 1 only if all inputs are 1. A dot (.) is used to show the AND operation i.e. (A.B). The symbolic representation and truth table of the 2-input AND gate are given below: OR Gate: A multi-input circuit in which the output is 1 when any input is 1. A plus (+) is used to show the OR operation i.e. (A+B). The symbolic representation and truth table of 2-input OR gate are given below: NOT Gate: The output is 0 when the input is 1, and the output is 1 when the input is 0. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The symbolic representation and truth table of an inverter are given below: NAND Gate: AND followed by an INVERTER. The output of a NAND gate is high if any of the inputs are low. It is also known as universal gate. The symbolic representation and truth table of 2-input NAND gate are given below: NOR Gate: OR followed by inverter. The outputs of a NOR gate is low if any of the inputs are high. It is also known as universal gate. The symbolic representation and truth table of 2-input NOR gate are given below: Ex-OR Gate: The output of the Exclusive-OR gate is 0 when its two inputs are the same and its output is 1 when its two inputs are different. X-OR gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An encircled plus sign ( ) is used to show the XOR operation. The symbolic representation and truth table of 2-input XOR gate are given below:  Ex-NOR Gate: The output of the Exclusive-NOR gate, is 1 when its two inputs are the same and its output is 0 when its two inputs are different. X-NOR gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is even. An encircled dot sign is used to show the Ex-NOR operation. The symbolic representation and truth table of 2-input XNOR gate are given below: Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 3 Procedure 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva 1. How many AND gates are required to realize Y = CD + EF + G? questions 2. How many NAND gates are required to design a XOR gate? Draw XOR gate using NAND gate. 3. Which gates are the universal gates? Why these gates are called universal gates?  Experiment Number < 2> 1 Aim / Implement Half Adder, Full Adder, Half Subtractor and Full Subtractor. Objective / problem statement sample Inputs for Half Adder and Half Subtractor input A=0, B=1 Inputs for Full Adder and Full Subtractor A=0, B=1, C=1 expected Output of Half Adder output Sum S= 1, Carry C=0 Output of Half Subtractor Diff D= 1, Borrow Bo =1 Output of Full Adder Sum S= 0, Carry C=1 Output of Full Subtractor Diff D= 0, Borrow Bo =1 2 Theory Half Adder: The Half Adder is a combinational digital circuit that adds two binary digits and produces two outputs as Sum(S) and Carry (C). The circuit, Block diagram and truth table of Half Adder are shown below: Full Adder: The Full Adder is a combinational digital circuit that adds three binary digits and produces two outputs as Sum (S) and Carry (Cout). The first two inputs are A and B and the third input is an input carry designated as Cin. The circuit diagram and Truth Table of a full adder are given below: Input(A) Input(B) Input( Cin) Sum(S) Carry(Cout) 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Half Subtractor: The Half-Subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, A (minuend) and B (subtrahend) and two outputs D (difference) and Bo (borrow). The circuit diagram and Truth Table of a half subtractor are given below: Inputs Outputs Input(A) Input(B) Diff (D) Borrow (Bo) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Full Subtractor: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate. The circuit diagram and Truth Table of a full subtractor are given below:  Input(A) Input(B) Input( C) Diffence Borrow(Bout) D 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva Draw the full adder using half adders. questions Draw the full subtractor using half subtractor. What is a major limitation of a half adder?  Experiment Number < 3 > 1 Aim / Objective / problem Implement 3-bit parallel Binary Adder/Subtractor. statement sample input A2 A1A0= 110 B2B1B0= 101 expected output When M=0, S2S1S0 = 011, C3= 1 When M=1, S2S1S0 = 001 C3 = 1 2 Theory Binary Adder/Subtractor: A 3-bit Binary Adder-Subtractor is a digital circuit for both addition and subtraction of two 3-bit binary numbers in one circuit itself. The operation being performed depends upon the binary value the control signal M. The circuit consists of 3 full adders. There is a control line M that holds a binary value of either 0 or 1. M=0 determines that the operation is addition. M=1 determines that the operation is subtraction. XOR gate complements its input if the other input is 1. The XOR gate properties given below. X  1 = X’ X  0 =X The 3-bit Binary Adder/Subtractor is shown below: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions How many full adders and XOR gates are required to make 4-bit Binary Adder/Subtractor? What is the disadvantage of a ripple adder? Draw the 4-bit parallel Binary Adder/Subtractor  Experiment Number < 4 > 1 Aim / Implement 3-bit carry look-ahead adder. Objective / problem statement sample A2 A1A0= 110 input B2B1B0= 101 expected S2S1S0 = 011, C3= 1 output 2 Theory Carry look ahead Adder: Carry look-ahead adder utilizes the logic gates to look at the lower order bits of augmend and addend to see if a higher order carry is to be generated or not. Carry look-ahead uses the two concepts of carry propagate and carry generate functions. This adder uses the following equations for ith stage: Carry propagate Pi=Ai Bi Carry generate Gi=Ai.Bi Sum Si= Pi Ci Carry Ci+1=Gi+Pi.Ci The circuit diagram of 3-bit Carry Look-Ahead Adder is shown in the following figure: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator lnk. 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva 1. What property distinguishes a look-ahead-carry adder from ripple adder? questions 2. What are the two functions Carry look-ahead logic uses to create carry look-ahead generator circuit? 3. What is carry propagation delay?  Experiment Number < 5 > 1 Aim / Implement 4-bit Binary -to -Gray, Gray -to -Binary code converter. Objective / problem statement sample input Input: For circuit 1: Binary code (B3B2B1B0) = 0101 Input: For circuit 2: Gray code (G3G2G1G0)= 0111 expected Output: For circuit 1: Gray code (G3G2G1G0)= 0111 output Output: For circuit 2: Binary code (B3B2B1B0) = 0101 2 Theory Gray Code: Gray code is a binary numeral system where two successive values differ in only one bit. Binary to Gray: Binary to gray code converter is a combinational circuit that converts a binary number into a gray code. The circuit diagram of Binary to Gray Converter is shown in the following figure: Gray to Binary: Gray to binary code converter is a combinational circuit that converts a gray code into binary code. The circuit diagram of Gray to binary code converter is shown in the following figure: Truth table for conversion:  S. No Binary Gray code code (B3B2B1B0) (G3G2G1G0) 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 8 1000 1100 9 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 15 1111 1000 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions What is the property of gray code? What are the applications of gray code? What are the weighted and un-weighted codes? Is gray code weighted?  Experiment Number < 6> 1 Aim / Objective / Implement a 2x2 Binary Multiplier. problem statement sample input Inputs : A1A0= 110 B1B0= 111 expected output P5P4P3P2P1P0 = 101010 2 Theory Binary multiplier: A binary multiplier is a combinational digital circuit to multiply two binary numbers. The binary multiplication of two 2-bit numbers A (A1 A0) and B (B1 B0) can be performed as given in the following image The circuit diagram of 3x3 bit binary multiplier has been shown in the following image. 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions Draw 4x4-Binary Multiplier. How many full adders and AND gates are will be required to draw 4x3 binary multiplier? How many bits will in the result of multiplication of M-bit and N-bit numbers?  Experiment Number < 7 > 1 Aim / Objective / Implement (4 to 2) line and (8 to 3) line Encoders. problem statement sample input Input for (4 to 2) line Encoder: D0D1D2D3 =0001 Input for (8 to 3) line Encoder: D0D1D2D3D4D5D6D7 = 00010000 expected output Output for (4 to 2) line Encoder: AB=11 Output for (8 to 3) line Encoder: ABC=011 2 Theory Encoder: An Encoder is a combinational circuit that has maximum of 2n input lines and ‘n’ output lines; hence it encodes the information from 2n inputs into an n-bit code. It will produce a binary code equivalent to the input, which is active High. (4 to 2) line Encoder: The 4 to 2 Encoder consists of four inputs D0 D1 D2 D3, and two outputs A and B. (4 to 2) Encoder encodes the information from 4 inputs into a 2-bit code. The circuit diagram and truth table of (4 to 2) line Encoder are shown below: Inputs Outputs D0 D1 D2 D3 A B 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 (8 to 3) line Encoder: The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: D7 to D0 and 3 outputs A, B and C. Each input line corresponds to each octal digit and three outputs generate corresponding binary code. The circuit diagram and truth table of (8 to 3) line Encoder are shown below:  Truth table for (8 to 3) line Encoder: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions What is Priority Encoder? What is decimal to BCD encoder? What are the applications of an encoder circuit?  Experiment Number < 8 > 1 Aim / Objective / Implement (2 to 4) line and (3 to 8) line Decoders. problem statement sample input Input for (2 to 4) line decoder: B1B0=11 Input for (3 to 8) line decoder: ABC=011 expected output Output for (2 to 4) line Encoder: D0D1D2D3 =0001 Output for (3 to 8) line Encoder: D0D1D2D3D4D5D6D7 = 00010000 2 Theory Decoder: In Digital Electronics, discrete quantities of information are represented by binary codes. A binary code of n bits is capable of representing up to 2n distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. (2 to 4) Decoder: The (2 to 4) decoder consists of two inputs B1and B0, and four outputs D0 D1 D2 D3. (4 to 2) decoder decodes the information from 2 inputs into a 4-bit code. The circuit diagram and truth table of (2 to 4) line decoder are given below: Truth Table for (2 to 4) line decoder: Inputs Outputs B1 B0 D0 D1 D2 D3 0 0 1 0 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 (3 to 8) line DECODER: The (3 to 8) decoder consists of three inputs A, B, and C, and eight outputs D0 D1 D2 D3 D4D5D6D7. (3 to 8) decoder decodes the information from 2 inputs into a 4-bit code. The circuit diagram and truth table of (2 to 4) line decoder are given below: Truth Table of (3 to 8) line DECODER: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions Draw the 3x8 decoder using 2x4 decoders. What is a binary decoder? What are the applications of a decoder?  Experiment Number < 9 > 1 Aim / Objective / problem Implement 4x1 and 8x1 Multiplexers. statement sample input Inputs For 4x1Mux: S1S0 = 00, Inputs For 8x1Mux: S2S1S0 = 000 expected output When I0=0, then Y=0 When I0=1, then Y=1 {in both the circuits} 2 Theory Multiplexer: Multiplexers are circuits that can select one of many inputs. 4x1 Multiplexer: 4:1-Mux has 4 inputs with only 1 output. It has 2 data selector inputs namely S0 and S1, at which the control bits are applied. I 0, I1, I2, and I3 represent the inputs bits. Only one of these will be transmitted to the output. But which one of the inputs will be transmitted will depend on the values of the controls. The selection table is given below: SELECTION INPUT OUTPUT S.No S1 S0 Y 1. 0 0 I0 2. 0 1 I1 3. 1 0 I2 4. 1 1 I3 The following circuit diagram shows 4x1 multiplexer:  8x1 Multiplexer: It has 8 inputs with only 1 output Y. It has 3 data selector inputs namely S0, S1, and S2 at which the control bits are applied. I0, I1, I2, I3, I4, I5, I6, and I7 represent the inputs bits. Only one of these will be transmitted to the output Y. But which one of the inputs will be transmitted will depend on the values of the controls. The circuit diagram and the selectiontable (truth table) of 8x1 Multiplexer are given below: SELECTION INPUT OUTPUT S2 S1 S0 Y 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1 1 0 I6 1 1 1 I7 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section  5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions 1. Draw the block diagram of 8 input multiplexer using 2-input multiplexer, 16 input multiplexer using 2-input multiplexer. 2. What are the applications of a multiplexer? 3. Implement the following function using 4x1 Mux. F(A, B, C) =∑ (2, 4,7)  Experiment Number < 10> 1 Aim / Objective / problem Implement 1x4 and 1x8 De-multiplexers. statement sample input Inputs For 1x4 De-Mux: S1S0 = 00, Inputs For 1x8 De-Mux: S2S1S0 = 000 expected output When I=0, then Y0=0 When I=1, ten Y0=1 2 Theory Demultiplexer: A demultiplexer is a combinational logic circuit with an input line, 2 n output lines and n select lines. It routes the information present on the input line to any of the output lines. The output line that gets the information present on the input line is decided by the bit status of the selection lines. 1x4 Demultiplexer: It has only data input I with 4 outputs namely Y0, Y1, Y2, and Y3. It has two data selector inputs namely S0 and S1, at which control bits are applied. The data bit is transmitted to any of the data bit Y0, Y1, Y2, and Y3 of the output lines. Which particular output line will be chosen will depend on the value of S1 and S0 the control input. The circuit diagram and the selection table (truth table) of 1x4 Demultiplexer are given below: Selection table: INPUT OUTPUT S1 S2 I Y0 Y1 Y2 Y3 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1x8 Demultiplexer: It has only data input I with 8 outputs namely Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7. It has three data selector inputs namely S0, S1 and S2, at which control bitsare applied. The data bit is transmitted to any of the Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 output lines. Which particular output line will be chosen will depend onthe value of S0, S1, and S2 the control input. The circuit diagram and the selection table (truth table) of 1x8 Demultiplexer are given below:  Selection Table Selection Input Output Selected S2 S1 S0 Y 0 0 0 Y0 0 0 1 Y1 0 1 0 Y2 0 1 1 Y3 1 0 0 Y4 1 0 1 Y5 1 1 0 Y6 1 1 1 Y7 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions 1. Draw a 1x8 demultiplexer using 1x4-demultiplexer. 2. Why a demultiplexer is called a data distributor? 3. How many selection lines are required in 1x64 demultiplexer.  Experiment Number < 11 > 1 Aim / Objective / Verify the characteristic/state tables of SR and D FLIP-FLOPS using NAND gates. problem statement sample input Input for SR Flip Flop: S=1, R=0 Input for D Flip Flop: D=1, En=1, expected output Q=1 { output for both the circuits} 2 Theory Flip Flop: Flip Flop is a sequential digital circuit that stores one bit. Types of the flip flops are :  SR Flip Flop  D Flip Flop  JK Flip Flop  T Flip Flop  Master-Slave JK Flip Flop SR Flip Flop SR flip flop is a circuit with two cross coupled NAND gates or NOR gates, and two inputs labeled S for set and R for Reset. The flip flop has two useful states. When output Q=1 and Q’=0 the flip flop is said to be in set state and when output Q=0 and Q’=1, it is in the reset state. Outputs Q and Q’ are normally complement of each other. However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 occurs. If both the inputs are then switched to 0 simultaneously, the device will enter an unpredictable or undefined state. In practical applications, setting both inputs to 1 is forbidden. The logic diagram of SR flip flop using NAND gate and its characteristic table are given below: D Flip Flop: The D input goes directly to the S input and its complement is applied to R input. As long as the enable is at 0, the cross-coupled SR latch has both inputs at the level 1 and the circuit cannot change state regardless of the value of D. The D input is sampled when En =1. If D =1, the Q output goes to 1, placing the circuit in the set state. If D=0, output Q goes to 0, placing the circuit in the reset state. The logic diagram of D flip flop using NAND gate and its characteristic table are given below: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and create a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva questions 1. What is difference between the flip flop and latch? 2. Draw the SR flip flop and D flip flop using NOR gates 3. What is a sequential digital circuit?  Experiment Number < 12 > 1 Aim / Design a 2-bit Arithmetic Logic Unit. Objective / problem statement sample S1S0=00 input A1A0= 11 B1B0= 01 expected Output of Arithmetic Unit: output When C0 = 0 D1D0=00, C2=1 When C0 = 1 D1D0= 01, C2=1 Output of Logic Unit : E0 = A0.B0 = 1 2 Theory Arithmetic Unit: The circuit diagram of arithmetic unit given below can perform the arithmetic microoperations listed in the given table. By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic operations. The diagram of a 4-bit arithmetic circuit shown below. It has two full adders and two multiplexers for selecting different operations. There are two 2-bit inputs A and B and 2-bit output D. the input A directly goes to X inputs of the binary adders. The multiplexer takes input B, Complement of B, 0 and 1 as input. The selection of inputs is controlled by S1 and S0 selection lines. The output of the binary adder is calculated by D = A + Y+ Cin. The possible generated microperations using this equation for different combinations of inputs are given in the arithmetic function table. The arithmetic function table: One Stage of Logic Unit: One stage of logic unit given in the following figure generates the four basic logic microoperations. It consists of four gates and a multiplexer. The outputs of the logic gates are applied to the input of multiplexer. The selection inputs S1 and S0 choose one of the data inputs. The diagram of one stage of logic unit and the corresponding function table are given below:  The Final ALU circuit design: 3 Procedure Steps: 1. Start the simulator by using https://circuitverse.org/simulator link 2. Design the circuit as shown in the theory section. 3. Set the inputs as shown in the Input section 4. And verify the output as mentioned in the output section 5. Take the screenshot and a PDF document 6. Upload this PDF document on the given assignment link onto the moodle. 4 Viva 1. Draw the 4-bit arithmetic unit: questions 2. Register A holds the 8-bit binary 11011001. Determine the B operand and the logic microoperation to be performed in order to change the value in A to 01101101 3. What is the purpose of ALU?