Lecture 1 - Computer Architecture-مدمج PDF

Computer Science Dep. MET 2024-2025 Computer Architecture 2024/2025 Lecture 1 Assis. Prof. Dr. Elmahdy Maree CH1: Computer Architecture and Organization Learning Objectives Upon completion of this lectu...

Computer Science Dep. MET 2024-2025 Computer Architecture 2024/2025 Lecture 1 Assis. Prof. Dr. Elmahdy Maree CH1: Computer Architecture and Organization Learning Objectives Upon completion of this lecture, you will be able to: ◆ Describe the design of digital basic building blocks Assis. Prof. Dr. Elmahdy Maree  Intrduction to Computer Architecture and Organization * Computer architecture Refers to those attributes of a system visible to a programmer or those attributes that have a direct impact on the logical execution of a program. Examples of architectural attributes Includes the instruction set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory. * Computer organization; Refers to the operational units and their interconnections that realize the architectural specifications. Organizational attributes Includes those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used. Lecture 2: Comp. Org. and Arch. CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 2: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks 1. Registers 2. COUNTERS 3. BUS 4. RAMS Lecture 2: Comp. Arch. and Org. Digital Logic and Computer Architecture MET 2024-2025 Lecture 2: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 D Flip flop Function Table Symbol : Equations Lecture 1: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 T Flip flop Function Table Symbol : Lecture 1: Flip Flops Digital Logic and Computer Architecture MET 2024-2025 JK Flip flop Function Table Symbol : Lecture 12: Flip Flops CH 1: Digital Building Blocks (Registers, Counters,.) Registers REGISTERS  CH 1: Digital Building Blocks (Registers, Counters,.) Buffer Registers Registers are a type of computer memory built directly into the processor or CPU (Central Processing Unit) that is used to store and manipulate data during the execution of instructions. A register may hold an instruction, a storage address, or any kind of data BUFFER REGISTERS  BUFFER REGISTERS Buffer register. Symbol : BUFFER REGISTERS  BUFFER REGISTERS Controlled buffer register with parallel load. Symbol : Assis. Prof. Dr. El Mahdy Maree Controlled Buffer Registers  BUFFER REGISTERS Controlled buffer register. Hardware Implementation : Controlled Buffer Registers  Three-State Registers NORMALLY OPEN Normally open switch NORMALLY CLOSED Normally closed switch. Three-state buffer register  Three-State Registers The main application of three-state switches is to convert the two-state output of a register to a three-state output. Symbol : Three-state buffer register  Shift Registers Shift-left register. Symbol : Shift-right register. Shift Shift Registers -left timing diagram.  CH 1: Digital Building Blocks (Registers, Counters,.) BUS-ORGANIZED COMPUTERS Lecture 2: Comp. Arch. and Org.  Bus-Organized Computers A bus is a group of wires that transmit a binary word Bus An abbreviated form of the bus example Bus Assis. Prof. Dr. El Mahdy Maree Questions Assis. Prof. Dr. Elmahdy Maree THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 2 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 2: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks 1. Registers 2. BUS System 3. COUNTERS 4. RAMS Lecture 2: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) COUNTERS A. SYNCHRONOUS COUNTERS B. ASYNCHRONOUS (RIPPLE) COUNTERS Lecture 2: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) SYNCHRONOUS COUNTERS Lecture 2: Comp. Arch. and Org.  CH 1: Digital Building Blocks (Registers, Counters,.) Design of Sequential Circuit Example 1: Design a 3 bit Counter (Using “T” FF) which counts in binary form as follows; 000, 001, 010, … 111, 000, 001, … Solution 2- State diagram: Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 4- State Table: Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 5- K-Map for FFs inputs and circuit Outputs + + + Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 5- K-Map for FFs inputs and circuit Outputs Lecture 2: Sequential Circuit  CH 1: Digital Building Blocks (Registers, Counters,.) 6- Circuit diagram: Symbol : Lecture 2: Sequential Circuit  SYNCHRONOUS COUNTERS SYNCHRONOUS COUNTERS Ring Counters Many digital circuits participate during a computer run to fetch and execute instructions Symbol : Controlling a sequence of operations RING COUNTERS  RING COUNTERS IMPLEMENTATION SAP-1 ring counter Hardware Implementation RING COUNTERS CH 1: Digital Building Blocks (Registers, Counters,.) ASYNCHRONOUS (RIPPLE) COUNTERS Lecture 2: Comp. Arch. and Org.  RIPPLE COUNTER (Asy.) ASYNCHRONOUS (RIPPLE) COUNTERS -ve edge up counter (Asyn) Ripple counter design  ASYNCHRONOUS COUNTERS ASYNCHRONOUS (RIPPLE) COUNTERS Controlled ripple counter(up counter –ve edge) Symbol : SAP-1 program counter COUNTERS  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  CH 1: Memory System Memory System ROM RAM Lecture 2 Comp. Arch. and Org. CH 4: Memory System ROM Design Lecture 8 Comp. Arch. and Org.  CH 1: Memory System ROM Design Design 8 x 4 ROM. Lecture 2 Comp. Arch. and Org.  CH 1: Memory System Types of ROMs Mask Programmed ROM Programmed during manufacturing Programmable Read-Only Memory (PROM) Blow out fuses to produce ‘0’ Erasable Programmable ROM (EPROM) Erase all data by Ultra Violet exposure Electrically Erasable PROM (EEPROM) Erase the required data using an electrical signal Lecture 2 Comp. Arch. and Org.  CH 5 Memory System Cache Memory Lecture 2: Comp. Arch. and Org.  CH 5: Memory System The Memory Hierarchy 24 Lecture 2:Comp. Arch. and Org. Questions Assis. Prof. Dr. Elmahdy Maree THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 3 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 3: Comp. Org. and Arch.  Structure of IAS Computer A Top-Level View of Computer Interconnection IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) CH 1: Digital Building Blocks (Registers, Counters,.) Digital Building Blocks ALU Dsign Lecture 3: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) COUNTERS Lecture 3: Comp. Arch. and Org. CH 1: Digital Building Blocks (Registers, Counters,.) Lecture 3: Comp. Arch. and Org.  CH 2: ALU Design Adders 1. Binary Adder Half Adder Full Adder 2. Binary Subtraction 3.. BCD Adder Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Full Adder Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design 8 Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Carry Propagate Adder (CPA) Adding Two 4-Bits Numbers Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org. Carry Propagate Adder (CPA) Adding Two 8-Bits Numbers  CH 2: ALU Design Carry Propagate Adder (CPA) Adding Two 8-Bits Numbers Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Binary Adder / Subtractor Lecture 3 Comp. Arch. and Org.  CH 2: ALU Design Binary Adder / Subtractor x3 x2 x1 x0 y3 y2 y1 y0 M A3 A2 A1 A0 B3 B2 B1 B0 Cy Binary Adder Ci S3 S2 S1 S0 F3 F2 F1 F0 M: Control Signal Mode: Add / Sub M=0 ➔ F = x + y M=1 ➔ F = x – y Lecture 3 Comp. Arch. and Org. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 4 Assis. Prof. Dr. Elmahdy Maree CH 1: Digital Building Blocks (Registers, Counters,.) A Top-Level View of Computer Function and Interconnection Lecture 3: Comp. Org. and Arch.  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann)  CH 2: Digital Building Blocks Digital Building Blocks ALU Dsign Lecture 4: Comp. Arch. and Org.  CH 2: ALU Design Multiplication 1. Unsigned Multiplication Fast Multiplication Multiplication with Shifter 2. Signed Multiplication Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication UNSIGNED INTEGERS the following figure illustrates the multiplication of unsigned binary integers, as might be carried out using paper and pencil. Several important observations can be made: Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Binary Multiplication (Fast Multiplier) Unsigned Binary Multiplication with Array of Full Adder Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Example: Multiply 11*13 using unsigned multiplication with shifter. Q0 Q0 Q0 Q0 Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Flowchart for Unsigned Binary Multiplication with Shifter Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Unsigned Multiplication with Shifter Hardware Implementation of Unsigned Binary Multiplication with Shifter Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Signed Binary Multiplication TWOS COMPLEMENT MULTIPLICATION Booth’s Algorithm Booth’s Algorithm for Twos Complement Multiplication Lecture 4: Comp. Architecture.  CH 2: ALU Design Multiplication Signed Binary Multiplication 7 Example: Multiply 7*3 using Booth’s Algorithm. -7 Arithmetic Shift Arithmetic Shift Arithmetic Shift Arithmetic Shift Lecture 4: Comp. Architecture. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 5 Assis. Prof. Dr. Elmahdy Maree  CH 2: Digital Building Blocks Digital Building Blocks ALU Dsign Lecture 4: Comp. Arch. and Org.  CH 2: ALU Design Division Unsigned Division Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 11012 Example1: calculate 102 – – – – Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 11012 Example1: calculate 102 – 0 0 1 0 – 0 0 1 0 – 0 0 1 0 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 1 11012 Example1: calculate 102 – 0 0 1 0 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 0 0 1 11012 Example1: calculate 102 – 0 0 1 0 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 1 0 11012 0 0 Example1: calculate 102 – 0 0 1 0 1 1 1 1 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 1 0 11012 0 0 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 1 0 0 0 1 0 – 0 0 1 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 0 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 0 11012 0 0 1 0 1 1 Example1: calculate 102 – 0 0 1 0 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 1 0 0 0 0 0 0 0 0 0 0 1 – 0 0 1 0 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 0 0 0 1 0 1 1 0 =𝑄+ – 0 0 1 0 𝐵 𝐵 11012 Example1: calculate 102 1 1 1 1 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 0 0 1 0 0 0 0 0 0 0 0 1 – 0 0 1 0 1 1 1 1 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 0 0 0 1 0 1 1 0 =𝑄+ – 0 0 1 0 𝐵 𝐵 11012 Example1: calculate 102 1 1 1 1 Q 0 0 1 1 – 0 0 1 0 0 0 0 1 0 0 1 0 – 0 0 1 0 Note: if last result is negative(i.e. the most significant bit is 1) then the 0 0 0 0 remainder will be the minuend (i.e. 0 0 0 1 R value of A before subtraction) else – 0 0 1 0 (i.e. the most significant bit is 0) it will be the last result 1 1 1 1 Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) Cont’d 𝐴 𝑅 =𝑄+ 𝐵 𝐵 Legend N R B R B Cout Cin Cout Cin + D N R' D Difference 1 0 N Negative R' Lecture 5: Comp. Architecture.  CH 2: ALU Design Division Dividers (unsigned) with shifter Example: (7/3) Restoring Twos Complement Division Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating Point Numbers 1. Fixed point numbers 2. Floating point numbers Floating point addition and subtraction Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating point representation IEEE 754 32-bit floating-point representation (single precision) 1 bit 8 bits 23 bits ± Mantissa× 2Exponent Sign Mantissa Mantissa should be written using 24 bits in this form: 1.1011…….1 Most Significant Bit of the mantissa is always 1, so no need to store it Store just the fraction bits in 23-bit field Biased exponent: bias = 127 (011111112) Biased exponent = bias + exponent Lecture 5: Comp. Architecture.  CH 2: ALU Design Floating point representation Write -58.2510 in 32-bit floating point (IEEE754 32) 58.2510 = 111010.012 111010.012 = 1.11010012 × 25 Sign bit: 1 (negative) 8 exponent bits: (127 + 5) = 132 = 100001002 23 fraction bits: 110 1001 0000 0000 0000 0000 1 bit 8 bits 23 bits 1 100 0010 0 110 1001 0000 0000 0000 0000 Sign Exponent Fraction Lecture 5: Comp. Architecture. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 6 Assis. Prof. Dr. Elmahdy Maree CH3 : Processor Design Chapter (3) Processor Design  CH3 : Processor Design Basic Instruction Cycle Lecture 6: Comp. Arch. and Org.  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) Computer Components: Top-Level View Basic Instruction Cycle Basic Instruction Cycle  Computer Components: Top-Level View Hypothetical Machine Example 1: Assis. Prof. Dr. El Mahdy Maree If PC=300 and the memory contents is as shown in the figure, show the contents of the registers and memory during the execution of three consecutive instructions. Basic Instruction Cycle Computer Components: Top-Level View Basic Instruction Cycle  CH 1: Digital Building Blocks Hypothetical Machine Example 2: Note that: 1. All data manipulations with RAM will be through AC, IR directly If PC=300 and the memory contents is as shown in the figure, show the contents of the registers and memory during the execution of three consecutive instructions. Basic Instruction Cycle CH 1: Digital Building Blocks Basic Instruction Cycle  CH 1: SAP-1 Control Word How each instruction is performed and executed in SAP 1 Fetch Decode 1. 2. 3. 4. 5. 6. PC→MAR PC+1→PC M[MAR]→IR IR[4-15]→ MAR M[MAR]→B AC+B→AC Lecture 2  SIMPLE - AS - POSSIBLE COMPUTER SAP 1 Architecture Lecture 6: Comp. Arch. and Org.  SIMPLE - AS - POSSIBLE COMPUTER It is required to design a typical computer with the following specifications: Characteristics of SAP-1 SAP-1 Memory It is required to design a typical computer with 16 x 8 RAM with only MAR attached to the memory chip. SAP-1 Instruction Set SAP-1 ALU The ALU contains AC and another register for executing the arithmetical operations. Lecture 6: Comp. Arch. and Org.: SAP-1 Architecture  CH 1: SAP -1 COMPUTER SAP-1 Architecture Control Unit Lecture 6: Comp. Arch. and Org.: SAP-1 Architecture THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 7 Assis. Prof. Dr. Elmahdy Maree CH3 : Processor Design Chapter (3) Processor Design  CH3 : Processor Design Basic Instruction Cycle Lecture 7: Comp. Arch. and Org.  Computer Components: Top-Level View IAS stands for Princeton Institute for Advanced Studies. (Von Neumann) Computer Components: Top-Level View Basic Instruction Cycle Basic Instruction Cycle  Computer Components: Top-Level View Hypothetical Machine Example 1: Assis. Prof. Dr. El Mahdy Maree If PC=300 and the memory contents is as shown in the figure, show the contents of the registers and memory during the execution of three consecutive instructions. Basic Instruction Cycle Computer Components: Top-Level View Basic Instruction Cycle  CH 1: Digital Building Blocks Hypothetical Machine Example 2: Note that: 1. All data manipulations with RAM will be through AC, IR directly If PC=300 and the memory contents is as shown in the figure, show the contents of the registers and memory during the execution of three consecutive instructions. Basic Instruction Cycle CH 1: Digital Building Blocks Basic Instruction Cycle  CH 1: SAP-1 Control Word How each instruction is performed and executed in SAP 1 Fetch Decode 1. 2. 3. 4. 5. 6. PC→MAR PC+1→PC M[MAR]→IR IR[4-15]→ MAR M[MAR]→B AC+B→AC Lecture 7  SIMPLE - AS - POSSIBLE COMPUTER SAP 1 Architecture Lecture 7: Comp. Arch. and Org.  SIMPLE - AS - POSSIBLE COMPUTER It is required to design a typical computer with the following specifications: Characteristics of SAP-1 SAP-1 Memory It is required to design a typical computer with 16 x 8 RAM with only MAR attached to the memory chip. SAP-1 Instruction Set SAP-1 ALU The ALU contains AC and another register for executing the arithmetical operations. Lecture 7: Comp. Arch. and Org.: SAP-1 Architecture  CH 1: SAP -1 COMPUTER SAP-1 Architecture Control Unit Lecture 7: Comp. Arch. and Org.: SAP-1 Architecture  CH 3:SIMPLE - AS - POSSIBLE COMPUTER Note that …..! Lecture 7: Comp. Arch. and Org.: SAP-1 Architecture  CH 1: SAP-1 Control Word The Control Word is a set of binary bits which forces the different elements of SAP 1 to perform a number of specific micro operations in one clock pulse. EXAMPLE: The control word is transferred during the different timing states which is called T states. Lecture 7: Comp. Arch. and Org.: Comp. Arch. and Org.  CH 3: SIMPLE - AS - POSSIBLE COMPUTERS SAP 1 Control Unit Design How dose SAP-1 work? Lecture 7: Comp. Arch. and Org.: SAP-1 Architecture  CH 3: SAP -1 COMPUTER SAP-1 Architecture Control Unit Lecture 2: SAP-1 Architecture  SAP-1 Instruction Cycle How dose SAP-1 work? The Fetch phase performed in three consecutive timing states T1, T2, T3 ❑ T1: Address State ❑ T2: Increment State ❑ T3: Memory State SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T1 : Address State The T1 state is called the address state because the address in the program counter (PC) is transferred to the memory address register (MAR) during this state. During the T1, EP and 𝑳𝑴 are active; all other control bits are inactive. This means that, during this state the controller sequencer is sending out a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T2 : Increment State The T2 state is called the increment state because the program counter (PC) is incremented. During the increment state, the controller-sequencer is producing a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T3 : Memory State The T3 state is called the memory state because the addressed RAM instruction is transferred from the memory to the instruction register. During the Memory state, the controller-sequencer is producing a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle SAP 1 Instruction Execution Cycle The instruction Execution phase of SAP-1 is performed in the next three states (T4, T5 , and T6 ). Each instruction of the instruction set has its own register transfer micro operations. SAP-1 FETCH Cycle  SAP-1 Instruction Cycle LDA Routine 4. T4 state: IR[4-8]→ MAR Assume that the instruction register has been loaded with LDA 9H: IR = 0000 1001 During the T4 state: The instruction field 0000 (Opcode) goes to the control unit where it will be decoded. But on the other hand, the address field 1001 will be loaded into the MAR. During the T4 state: 𝑬𝑰 and 𝑳𝑴 are active; all other control bits are inactive. SAP-1 Execution Cycle  SAP-1 Instruction Cycle 5. T5 state: M[MAR]→ AC During the T5 state: 𝑪𝑬 and 𝑳𝐴 go low. This means that the addressed data word in the RAM will be loaded into the accumulator on the next positive clock edge SAP-1 Execution Cycle  SAP-1 Instruction Cycle 6. T6 state of the LDA : nop T6 is a no-operation state so, all registers are inactive SAP-1 Execution Cycle  SAP-1 Instruction Cycle The timing diagram for the fetch and LDA routines SAP-1 Execution Cycle  SAP-1 Instruction Cycle The timing diagram for the fetch and LDA routines During the T1 state: EP and 𝐿𝑀 are active; the positive clock edge midway through this state will transfer PC→MAR. During the T2 state, CP is active and PC+1→PC on the positive clock edge. During the T3 state, 𝐶𝐸 and 𝐿𝐼 are active; this means that when the positive clock edge occurs, M[MAR]→IR. ------------------------------------------------- The LDA execution starts with the T4 state, where 𝐿𝑀 and 𝐸𝐼 are active; on the positive clock edge the MAR→IR[4-8]. During the T5 state, 𝐶𝐸 and 𝐿𝐴 are active; this means that M[MAR]→A on the positive clock edge. The T6 state of the LDA routine is a nop. SAP-1 Execution Cycle  SAP-1 Instruction Cycle ADD T4 state: ADD T5 state: ADD T6 state: OUT T4 state: OUT T5 state: OUT T6 state: PC A PC A MAR Add/SUB MAR Add/SUB RAM B RAM B IR O IR O CON CON D D No Operation No Operation SAP-1 Execution Cycle  SAP-1 Microprogram Microinstructions: The first three T states are always the fetch cycle in SAP-1. The CON words for the fetch cycle are: Listing of each macroinstruction and the microinstructions needed to carry it out. Questions Assis. Prof. Dr. Elmahdy Maree THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 8 Assis. Prof. Dr. Elmahdy Maree CH3 : Processor Design Chapter (3) Processor Design  CH3 : Processor Design Basic Instruction Cycle Lecture 8: Comp. Arch. and Org. Computer Components: Top-Level View Basic Instruction Cycle Basic Instruction Cycle  CH 1: SAP-1 Control Word How each instruction is performed and executed in SAP 1 Fetch Decode 1. 2. 3. 4. 5. 6. PC→MAR PC+1→PC M[MAR]→IR IR[4-15]→ MAR M[MAR]→B AC+B→AC Lecture 8  SIMPLE - AS - POSSIBLE COMPUTER SAP 1 Architecture Lecture 8: Comp. Arch. and Org.  SIMPLE - AS - POSSIBLE COMPUTER It is required to design a typical computer with the following specifications: Characteristics of SAP-1 SAP-1 Memory It is required to design a typical computer with 16 x 8 RAM with only MAR attached to the memory chip. SAP-1 Instruction Set SAP-1 ALU The ALU contains AC and another register for executing the arithmetical operations. Lecture 8: Comp. Arch. and Org.: SAP-1 Architecture  CH 1: SAP -1 COMPUTER SAP-1 Architecture Control Unit Lecture 8: Comp. Arch. and Org.: SAP-1 Architecture  CH 3:SIMPLE - AS - POSSIBLE COMPUTER Note that …..! Lecture 8: Comp. Arch. and Org.: SAP-1 Architecture  CH 1: SAP-1 Control Word The Control Word is a set of binary bits which forces the different elements of SAP 1 to perform a number of specific micro operations in one clock pulse. EXAMPLE: The control word is transferred during the different timing states which is called T states. Lecture 8: Comp. Arch. and Org.: Comp. Arch. and Org.  CH 3: SIMPLE - AS - POSSIBLE COMPUTERS SAP 1 Control Unit Design How dose SAP-1 work? Lecture 8: Comp. Arch. and Org.: SAP-1 Architecture  CH 3: SAP -1 COMPUTER SAP-1 Architecture Control Unit Lecture 2: SAP-1 Architecture  SAP-1 Instruction Cycle How dose SAP-1 work? The Fetch phase performed in three consecutive timing states T1, T2, T3 ❑ T1: Address State ❑ T2: Increment State ❑ T3: Memory State SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T1 : Address State The T1 state is called the address state because the address in the program counter (PC) is transferred to the memory address register (MAR) during this state. During the T1, EP and 𝑳𝑴 are active; all other control bits are inactive. This means that, during this state the controller sequencer is sending out a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T2 : Increment State The T2 state is called the increment state because the program counter (PC) is incremented. During the increment state, the controller-sequencer is producing a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle ❑ T3 : Memory State The T3 state is called the memory state because the addressed RAM instruction is transferred from the memory to the instruction register. During the Memory state, the controller-sequencer is producing a control word SAP-1 FETCH Cycle  SAP-1 Instruction Cycle SAP 1 Instruction Execution Cycle The instruction Execution phase of SAP-1 is performed in the next three states (T4, T5 , and T6 ). Each instruction of the instruction set has its own register transfer micro operations. SAP-1 FETCH Cycle  SAP-1 Instruction Cycle LDA Routine 4. T4 state: IR[4-8]→ MAR Assume that the instruction register has been loaded with LDA 9H: IR = 0000 1001 During the T4 state: The instruction field 0000 (Opcode) goes to the control unit where it will be decoded. But on the other hand, the address field 1001 will be loaded into the MAR. During the T4 state: 𝑬𝑰 and 𝑳𝑴 are active; all other control bits are inactive. SAP-1 Execution Cycle  SAP-1 Instruction Cycle 5. T5 state: M[MAR]→ AC During the T5 state: 𝑪𝑬 and 𝑳𝐴 go low. This means that the addressed data word in the RAM will be loaded into the accumulator on the next positive clock edge SAP-1 Execution Cycle  SAP-1 Instruction Cycle 6. T6 state of the LDA : nop T6 is a no-operation state so, all registers are inactive SAP-1 Execution Cycle  SAP-1 Instruction Cycle The timing diagram for the fetch and LDA routines SAP-1 Execution Cycle  SAP-1 Instruction Cycle The timing diagram for the fetch and LDA routines During the T1 state: EP and 𝐿𝑀 are active; the positive clock edge midway through this state will transfer PC→MAR. During the T2 state, CP is active and PC+1→PC on the positive clock edge. During the T3 state, 𝐶𝐸 and 𝐿𝐼 are active; this means that when the positive clock edge occurs, M[MAR]→IR. ------------------------------------------------- The LDA execution starts with the T4 state, where 𝐿𝑀 and 𝐸𝐼 are active; on the positive clock edge the MAR→IR[4-8]. During the T5 state, 𝐶𝐸 and 𝐿𝐴 are active; this means that M[MAR]→A on the positive clock edge. The T6 state of the LDA routine is a nop. SAP-1 Execution Cycle  SAP-1 Instruction Cycle ADD T4 state: ADD T5 state: ADD T6 state: OUT T4 state: OUT T5 state: OUT T6 state: PC A PC A MAR Add/SUB MAR Add/SUB RAM B RAM B IR O IR O CON CON D D No Operation No Operation SAP-1 Execution Cycle  SAP-1 Microprogram Microinstructions: The first three T states are always the fetch cycle in SAP-1. The CON words for the fetch cycle are: Listing of each macroinstruction and the microinstructions needed to carry it out.  SIMPLE - AS - POSSIBLE COMPUTERS SAP-1 SAP1 Hardware With control matrix and decoder SAP-1 Schematic Diagram Complete Clock Circuit  PC MAR RAM IR  Ring counter Ring Counter Data Control BUS BUS CU Data BUS BUS  Data BUS BUS Data AC ALU ALU ‫ والـ‬B ‫وصلة مباشرة بين‬ BUS BUS Control Control  Control BUS B DATA BUS O CH 1: Digital Building Blocks (Registers, Counters,.) Student Work 1. Each student should prepare a simulation for one of the following circuits using Logisim: 1- SAP 1 ALU + Bus+ Registers circuit. 2- SAP 1 RAM + Bus+ Registers circuit. 3- SAP 1 CU + Bus+ Registers circuit. 2. Each team should prepare a simulation for SAP 1 3. Each team implements the hardware circuit which has been assigned to them. Lecture 8: Comp. Arch. and Org. SAP-1 Simulation using Logisim SAP-1 Simulation SIMPLE - AS - POSSIBLE COMPUTERS SAP-2  SAP-2 SAP-2 specifications 1. SAP-2 Instruction Set 2. Input Serial input keyboard Parallel input 3. Output display Serial output Display Parallel output 4. Flags Zero Sign 5. More registers 4 registers 6. Large Memory(64k) ROM RAM 7. Instruction format Lecture 8: Comp. Arch. and Org.  Instruction Set These are the 8080/8085 op codes. Lecture 6: Comp. Arch. and Org.  SAP-2 Lecture 8: Comp. Arch. and Org. SIMPLE - AS - POSSIBLE COMPUTERS SAP-3  SAP-3 More Instructions New SAP II More Registers has been introduced More Flags in the Flag register. Stack and Addressing modes issues has been introduced in SAP III Lecture 8: Comp. Arch. and Org.  SAP-3 Lecture 8: Comp. Arch. and Org. THANK YOU Computer Science Dep. MET 2024-2025 CS 311 Computer Architecture 2024/2025 Lecture 9 Assis. Prof. Dr. Elmahdy Maree CH5 : Memory System Chapter (5) Memory System CH 5: Memory System Memory System RAM ROM Lecture 9 Comp. Arch. and Org. CH 5: Memory System ROM Lecture 9 Comp. Arch. and Org. CH 5: Memory System ROM Design Lecture 9 Comp. Arch. and Org.  CH 5: Memory System ROM Design SAP 1 Address ROM Address ROM 0 A3 1 I3 A2 2 I2 3 A1 I1 4 A0 I0 5. Control ROM.. 1 E 15 D3 D2 D1 D0 6 Lecture 9 Comp. Arch. and Org.  CH 5: Memory System ROM Design SAP 1 Control ROM Address ROM 0 A3 1 I3 A2 2 I2 4 x 16 3 A1 I1 Decoder 4 A0 I0 5 Control ROM... 1 E 15 D15 D0 7 Lecture 9 Comp. Arch. and Org.  CH 5: Memory System Types of ROMs Mask Programmed ROM Programmed during manufacturing Programmable Read-Only Memory (PROM) Blow out fuses to produce ‘0’ Erasable Programmable ROM (EPROM) Erase all data by Ultra Violet exposure Electrically Erasable PROM (EEPROM) Erase the required data using an electrical signal 8 Lecture 9 Comp. Arch. and Org.  CH 5: Memory System RAM Design Internal Memory Lecture 9:Comp. Arch. and Org.  CH 5: Memory System SDRAM DIMM (Dual In-line Memory RAM Design Modules): SDRAM stands for Synchronous Dynamic Random Access Memory. DIMMs allow the ability to have two rows of DRAM chips. SO DIMM (Small Outline DIMM): SO DIMMs are commonly used in notebooks and are about half the size of normal DIMMs. 11 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Memory Array 4X4 RAM Input Data 0 Address I1 BC BC BC BC Lines I0 2x4 1 Decoder BC BC BC BC 2 Memory BC BC BC BC Enable E 3 BC BC BC BC Read/Write Output Data Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Types of RAMs Lecture 9: Comp. Arch. and Org.  CH 5: Memory System Comparison between SRAM and DRAM Lecture 9: Comp. Arch. and Org.  CH 5 Memory System Cache Memory Lecture 9: Comp. Arch. and Org.  CH 5: Memory System The Memory Hierarchy 16 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Cache memory is designed to combine the memory access time of expensive, highspeed memory combined with the large memory size of less expensive, lower- speed memory. The concept is illustrated in the following figure. 17 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Main memory consists of up to 2n addressable words consist of of a number of fixed- length blocks of K words each. That is, there are M = 2n /K blocks in main memory. The cache consists of m blocks, called lines. Each line contains K words, plus a tag of a few bits. Each line also includes control bits. The control bits, such as a bit to indicate whether the line has been modified since being loaded into the cache. The line size is the length of a line, not including tag and control bits. Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Cache Read Operation RA=Read Address 19 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory 20 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Mapping Function Because there are fewer cache lines than main memory blocks, an algorithm is needed for mapping main memory blocks into cache lines. Further, a means is needed for determining which main memory block currently occupies a cache line. The choice of the mapping function dictates how the cache is organized. Three techniques can be used: Direct Mapping. Associative Mapping. set-associative Mapping. 21 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory: Direct Mapping. Each block of main memory maps into one unique line of the cache. The next m blocks of main memory map into the cache in the same fashion; that is, block Bm of main memory maps into line L0 of cache, block Bm+1 maps into line L1, and so on. 22 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory: Associative Mapping. ASSOCIATIVE MAPPING Associative mapping overcomes the disadvantage of direct mapping by permitting each main memory block to be loaded into any line of the cache. In this case, the cache control logic interprets a memory address simply as a Tag and a Word field. The Tag field uniquely identifies a block of main memory. To determine whether a block is in the cache, the cache control logic must simultaneously examine every line’s tag for a match.. 23 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Set Associative Mapping. Set- Associative Mapping is a compromise that exhibits the strengths of both the direct and associative approaches while reducing their disadvantages. 24 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Replacement Algorithms Once the cache has been filled, when a new block is brought into the cache, one of the existing blocks must be replaced. For direct mapping, there is only one possible line for any particular block, and no choice is possible. For the associative and set associative techniques, a replacement algorithm is needed. Least recently used (LRU): Replace that block in the set that has been in the cache longest with no reference to it First- In- First- Out (FIFO): Replace that block in the set that has been in the cache longest. Least Frequently Used (LFU): Replace that block in the set that has experienced the fewest references. Random: A technique not based on usage is to pick a line at random from among the candidate lines. To achieve high speed, such an algorithm must be implemented in hardware. 25 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Write Policy write through. All write operations are made to main memory as well as to the cache, ensuring that main memory is always valid. write back With write back, updates are made only in the cache. When an update occurs, a dirty bit, or use bit, associated with the line is set. Then, when a block is replaced, it is written back to main memory if and only if the dirty bit is set. 26 Lecture 9:Comp. Arch. and Org.  CH 5: Memory System Cache Memory Muli-Level cache 27 Lecture 9:Comp. Arch. and Org. THANK YOU