CMOS Processing PDF

# Session 12: CMOS processing ## CMOS processing: introduction - Next slides: typical 130nm twin-well dual damascene copper based CMOS process. - Some simplifications are used, real processes have often more steps regarding tuning of well doping profiles, Source/drain doping profiles, etc. - Furt...

# Session 12: CMOS processing ## CMOS processing: introduction - Next slides: typical 130nm twin-well dual damascene copper based CMOS process. - Some simplifications are used, real processes have often more steps regarding tuning of well doping profiles, Source/drain doping profiles, etc. - Furthermore, each company has his own CMOS processing sequence, with variations related to the process shown in this section. - Drawings are taken and modified from animation: **http://www.silicon-edge.co.uk/swf/cmos.swf** **Process steps:** 1. Start with doped Si wafer 2. Label wafer labeling, wafer cleaning 3. Fabrication of zero-level alignment marks for later litho steps ## CMOS: well isolation: shallow trench isolation (STI) **Well insulation:** - Older processes: LOCOS isolation - Newer CMOS (< 250nm nodes): shallow trench isolation (STI) **Process steps:** 1. Deposition of pad oxide (thermal oxidation) 2. Deposition of nitride layer (low pressure CVD) 3. Resist coating, STI lithography 4. Etch of nitride and oxide (RIE) 5. trench etch in Si with nitride as hard mask (RIE) - RIE = reactive ion etching 6. STI filling: - thin barrier oxide (CVD deposition) or thermal growth of liner oxide to repair silicon and to round off sharp corners - thick oxide (PECVD TEOS) 7. CMP, stop on nitride 8. Remove nitride hardmask and pad oxide (wet etch) - some STI topography is left due to thickness of nitride layer ## CMOS: well formation - Well formation: in real processes, the well is often a complex composition of various implantations in order to obtain a dedicated doping profile → so called 'well engineering' - Remark: sometimes the well formation happens before the well insulation (Locos, STI) is fabricated. **Process steps:** 1. Grow sacrificial oxide 2. Resist coat and well lithography 3. Phosphorous implantation for p-well doping 4. shallow p-implant to finetune Vt of later transistors (Vt-adjustment) 5. Strip resist 6. Coat resist, litho for n-well 7. implantation for n-well doping 8. shallow n-implant to finetune Vt of later transistors (Vt-adjustment) 9. Strip resist ## CMOS: well engineering 1. **uniformly doped well**: for older CMOS technologies, simple processing: - uniform doped well (diffusion + drive-in) which might be followed by extra implant for Vt adjustment (ion implantation with RTA). Wells are typically ~1um deep. 2. **For smaller CMOS technologies: super steep retrograde well (SSRW)** - after uniform well fabrication: extra implants to form a well with lower surface doping and higher doping just below surface. Typically heavy ions are used (slow diffusers): Indium (p-well) and Antimony or Arsenic (n-well). **Advantages of SSRW:** - higher carrier mobility in channel due to lower surface doping, hence increased drive current - suppression of short channel effects (VT roll-off, punch-through, drain induced barrier lowering) due to higher doping just below surface - suppression of latch-up ## CMOS: poly-Si gate formation **Process steps:** 1. Strip sacrificial oxide (wet etch) 2. Grow gate oxide: - gate oxide engineering: - thermal oxidation of a few nm of oxide - when gate oxide <4-5nm, tunneling of boron from p-poly gate in channel is possible: can be prevented by N2O incorporation in SiO2 (diffusion barrier) - for 45nm CMOS and smaller: 1nm SiO2 is needed → thermal oxide has limited quality when 1nm thick → use of high-к (high permittivity) gate oxides deposited by ALD (such as Al2O3, HfO2,..) Only technique with good enough quality that size 3. Poly-Si deposition (low pressure CVD) 4. Resist coat and gate litho 5. Poly-Si etch (RIE) 6. Strip resist 7. Rapid thermal anneal (RTA) ## CMOS: low doped drain (LDD) formation - Low Doped Drain (LDD) implants: essential when transistor dimensions become small. - LDD is a low doped shallow source/drain extension which will limit the otherwise very high local electrical field, which should result in 'hot carrier' generation. **Process steps:** 1. Resist coat and n-LDD litho 2. Resist coat and p-junction litho 3. p-type implantation: well counter-doping to form junctions and doping of poly-Si (ion implant + resist strip + RTA) ## CMOS: S/D junction fabrication: spacer formation **Process steps:** 1. Deposition of thin nitride layer 2. Deposition of thick oxide layer 3. Dry etch of oxide, stop RIE when oxide on horizontal surfaces is removed 4. Dry etch of nitride layer ## CMOS: S/D junction fabrication: implantation **Process steps:** 1. Resist coat, litho of n-type S/D junction and contact to n-well 2. N-type ion implantation to create highly doped junctions, and to dope polysilicon gate 3. Resist coat, litho of p-type S/D junction and contact to p-well 4. p-type ion implantation to create highly doped junctions, and to dope polysilicon gate 5. Remove thin gate oxide on top of source/drain (wet etch, thin layer removed from spacers too) ## Silicidation - salicide process - Source/drain and poly gate have still considerable resistivity → RC delays - higher conductance needed at top of S/D and gate local formation of silicides - Silicide: material with high conductivity formed by silicidation, which is the reaction of silicon with a transition metal such as Ti, Co, W, Ni - Salicide: self-aligned-silicidation (by the use of spacers) → see next slide **Silicidation process:** 1. Metal deposition (Ti, Co, W or Ni) 2. Heating (annealing): Si + metal convert to silicide SiO2 + metal does not convert 3. Removal of unreacted metal 4. Sometimes an extra higher temperature annealing is used to obtain a stable silicide material ## CMOS: silicide formation - salicide process **Process steps:** 1. Deposit metal for silicide formation (ie. Cobalt) 2. Deposit TiN to protect Co from oxidation at the metal layer surface during following annealing 3. Annealing: formation of CoSi2 on Si and poly-Si surfaces, but not on SiO2 4. Remove TiN (wet etch) 5. Remove unreacted Co (wet etch) 6. In many cases: extra anneal step to form low resistive and stable silicide layer ## Back-end-of-line processing (BEOL) for smaller CMOS technologies: CMP is used for planarization - Oldest CMOS technologies: no planarization in BEOL - Only a few metal layers were used, and the metal dimensions were large hence no severe problems due to topography - later: topography was problematic for the smaller dimension of metal patterns and contact/via holes, and more metal layers needed to be fabricated - (partial) planarization in BEOL is done by reflow of PSG or BPSG ('flowable' oxides: Boron-Phosphorus doped silicon glass, which flows at temperatures below 400C) or by spin-coating of oxide-like materials - Currently: conformal deposition of high quality inter-metal-dielectrics is used (good step coverage), followed by a CMP step ## CMOS: pre-metal dielectric **Process steps:** 1. Deposit thin nitride layer (CVD) 2. Deposit a thick pre-metal dielectric by CVD (such as, PSG = phosphorus-doped oxide) 3. Use CMP for planarization of pre-metal dielectric layer 4. Deposit SiC as hard mask for following RIE 5. Coating of resist, litho for contact hole etching ## CMOS: contact hole formation **Process steps:** 1. Dry etch of SiC hardmask 1 2. Dry etch of oxide, stop on nitride 3. Dry etch of nitride 4. Strip resist 5. Deposit Ti/TiN as barrier layer (diffusion barrier, adhesion promotion) by PVD 6. Tungsten deposition by CVD (optimized process for void-free filling of hole) - Tungsten: low resistivity 7. CMP to remove tungsten, stop on SiC hardmask 1 ## CMOS: Metallization by Damascene technology - Older technologies: - all metallization was done using aluminum, surrounded by oxide. only 2-3 metal layers were used - Later: more transistors and larger chips resulted in the need of more metal interconnects → more metal layers essential → 6 to 9 layers of metal (or even more) is now commonly seen. - Smaller CMOS technologies: resistivity of aluminum is too high, RC-delays of metallization levels was slowing down the CMOS performance - use of Cu metallization - use of alternative dielectric materials (low-k dielectrics) ## CMOS: Metallization by Damascene technology - use of Cu metallization → problem: small patterns of Cu can't be etched, no RIE possible - New metallization scheme: Damascene process **Comparison table:** |Conventional metal patterning | Damascene technology| |:-----------------------------|:-----------------------------------| |Metal Etch|Dielectric Etch| |Dielectric Deposition|Metal Deposition| |Dielectric Planarization (CMP)|Metal CMP| ## CMOS: M1 by single Damascene (1) **Process steps:** 1. Deposition of inter-metal dielectric (ie. TEOS CVD of oxide) 2. Deposition of hardmask 2 (ie. SiC CVD) 3. Resist coating, litho for first metal level 4. Etch hardmask 2 (RIE) 5. Etch inter-metal dielectric (RIE), stop on Tungsten and hardmask 1 6. Strip resist ## CMOS: M1 by single Damascene (2) **Process steps:** 1. Deposition of conductive barrier layer (prevents later diffusion of copper) 2. Deposition of thin Cu seed layer (sputtering) for next Cu plating step 3. Electroplating of thick Cu layer 4. CMP of Cu, stop on hardmask 2 ## CMOS-BEOL: dual Damascene for Via-1 & metal-2 fabrication **Process steps:** 1. Deposition of hardmask 3 (ie. SiC CVD) 2. Deposition of via-1 dielectric (ie. TEOS CVD of oxide, CVD of low-k material) 3. Deposition of hardmask 4 (ie. SiC CVD) ## CMOS-BEOL: dual Damascene (2) **Process steps:** 1. Deposition of 2nd inter-metal dielectric (ie. TEOS CVD of oxide) 2. Deposition of hardmask 5 3. Resist coat, litho for via-1 pattern 4. Etch hardmask 5 5. Strip resist (not shown) ## CMOS-BEOL: dual Damascene (3) **Process steps:** 1. Etch of 2nd inter-metal dielectric (RIE) using hardmask 5 and stop on hardmask 4 2. Resist coat, litho for metal-2 pattern (difficulty for litho: high topography) 3. Etch hardmask 4 and 5 (see red arrows: hardmask is removed) 4. Strip resist (not shown) ## CMOS-BEOL: dual Damascene (4) **Process steps:** 1. Etch of 2nd inter-metal dielectric and via-1 dielectric (RIE) using hardmask 5 and hardmask 4, and stop on hardmask 4 and 3 2. Etch of hardmask 3 and 4, but do not remove hardmask 5 (use of various materials with sufficient etch selectivity) 3. Deposition of conductive barrier layer (prevents later diffusion of copper) ## CMOS-BEOL: dual Damascene (5) **Process steps:** 1. Deposition of Cu seed layer for next Cu plating step 2. Cu electroplating to deposit thick Cu layer 3. CMP of Cu, stop on hardmask 5 → simultaneous fabrication of via-1 & metal-2 finished ## CMOS: BEOL: repetition of dual Damascene steps **Table:** |Layer |Description| |:------|:--------------| |V2 + M3|Dual Damascene| |V1 + M2|Dual Damascene| | M1 |Single Damascene| |CO |CO| |V7+ M8| | |V6+ M7| | |V5 + M6| | |V4 + M5| | |V3 + M4|Dual Damascene| |V2 + M3|Dual Damascene| |V1 + M2|Dual Damascene| | M1 |Single Damascene| |CO |CO| **Notes:** - Fabrication of all metal and via layers ## CMOS: fabrication of passivation and bondpads **Process steps:** 1. Deposition of passivation layers to protect chip during later packaging (CVD of oxide + (SiC) + nitride) 2. Litho + etch holes through passivation 3. Deposit Aluminum 4. Litho and etch of Aluminum to form bondpads ## CMOS in pictures - 32nm CMOS transistor with metal gate, Cu Damascene BEOL, A6 processor of Samsung Source: UBM Techinsights - BEOL process using Cu Damascene Courtesy UMC