Power Dissipation in CMOS PDF

Power Dissipation in CMOS P.K. Shetty, MSIS, MAHE 1 Single Channel Inverters NELS HMOS Pseudo-nMOS P  V3DD P  V3DD P  VDD P  V3DD P.K. Shetty, MSIS, MAHE 2 CMOS Logic (Inverter)...

Power Dissipation in CMOS P.K. Shetty, MSIS, MAHE 1 Single Channel Inverters NELS HMOS Pseudo-nMOS P  V3DD P  V3DD P  VDD P  V3DD P.K. Shetty, MSIS, MAHE 2 CMOS Logic (Inverter) No static leakage path exists for either 1 or 0 input. P.K. Shetty, MSIS, MAHE 3 Components of Power Dissipation  Dynamic Component (Pdyn) ◼ Switching p.d. (Psw) o Logic activity o Glitches ◼ Short-circuit p.d. (Psc)  Static Component (Pstat) ◼ Leakage p.d. Ptotal = Pdyn + Pstat For a small-geometry = (Psw + Psc) + Pstat IC diode, IS=1E-16. P.K. Shetty, MSIS, MAHE 4 Switching Power : Psw p P.K. Shetty, MSIS, MAHE 5  I R V P.K. Shetty, MSIS, MAHE 6 Switching Power : Psw P.K. Shetty, MSIS, MAHE 7  Switching Power : Psw  Gate output rising transition ◼ Energy stored in capacitor = CLVDD2/2 2 ◼ Energy dissipated in pMOS transistor = CLV DD/2  Gate output falling transition ◼ Energy dissipated in nMOS transistor = CLV2DD/2 2  Energy dissipated per transition = CLV DD  Total Power dissipation: Psw = CL V2DD / T P.K. Shetty, MSIS, MAHE 8 Lowering Switching Power: Capacitance: Clock Frequency: Function of Fan-out, Wire length Increasing and transistor sizes. Psw = CL V2DD fCLK  Supply voltage: Activity factor: Dropping with How often, on average, Successive generations do a node switch? P.K. Shetty, MSIS, MAHE 9  Activity factor Psw = CL V2DD fCLK  P.K. Shetty, MSIS, MAHE 10  Psw = CL V2DD fCLK   Even though power dissipation takes place in a channel resistance, in the equation above the resistance parameter is missing and the power is independent of resistance. Why? P.K. Shetty, MSIS, MAHE 11 Glitches  Glitches are temporary changes in the value of the output – unnecessary transitions.  Are caused due to the skew in the input signals to a gate. P.K. Shetty, MSIS, MAHE 12 P.K. Shetty, MSIS, MAHE 13 P.K. Shetty, MSIS, MAHE 14 Dynamic Gate Output Evaluate n-logic Inputs block Pre-charge CLK Waveform CLK P.K. Shetty, MSIS, MAHE 15 P.K. Shetty, MSIS, MAHE 16 Glitch Power Dissipation  Depending on the skew, the gate output voltage may perform a full swing or not.  An approximation of the energy drawn during the glitch is: Where ΔVn is the voltage swing of a sequence of n incomplete transitions within a period of T. P.K. Shetty, MSIS, MAHE 18 Components of Power Dissipation  Dynamic Component (Pdyn) ◼ Switching p.d. (Psw) o Logic activity o Glitches ◼ Short-circuit p.d. (Psc)  Static Component (Pstat) ◼ Leakage p.d. Ptotal = Pdyn + Pstat = (Psw + Psc) + Pstat P.K. Shetty, MSIS, MAHE 19 Short Circuit Power of a Transition: Psc P.K. Shetty, MSIS, MAHE 20  C A D B E P.K. Shetty, MSIS, MAHE 22 P.K. Shetty, MSIS, MAHE 23  24 P.K. Shetty, MSIS, MAHE  Peak Short Circuit Current For an unloaded inverter, assuming that tr = tf =   Increases with the size (or gain, β) of transistors  Increases with rise and fall times of input  Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down.  Decreases with load capacitance, CL  Largest when CL = 0 25 P.K. Shetty, MSIS, MAHE  Summary: Short-Circuit Power  Short-circuit power is consumed by each transition (increases with input transition time).  Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power).  Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when VDD ≤ |Vtp| + Vtn. P.K. Shetty, MSIS, MAHE 26  Solution:  Theorem – A CMOS gate consumes no short-circuit power when VDD ≤ Vtn + |Vtp|, i.e., supply voltage is lower than the sum of the threshold voltage magnitudes for the n and p channel MOSFETs.  Proof: The short-circuit conduction requires that a pull-up path through pMOS devices and a pull-down path through nMOS devices should be simultaneously on. If the common gate voltage for both devices is Vin, where 0 ≤ Vin ≤ VDD, then a necessary condition for short-circuit conduction is: Vtn ≤ Vin ≤ VDD – |Vtp| In order to make this condition impossible, we must ensure that the upper bound on Vin does not exceed the lower bound. Thus, VDD – |Vtp| ≤ Vtn 27 Therefore, VDD ≤ Vtn + |Vtp| Components of Power  Dynamic ◼ Signal transitions  Logic activity  Glitches ◼ Short-circuit  Static ◼ Leakage P.K. Shetty, MSIS, MAHE 28 Leakage Power: VDD Ground IG Gate R Source Drain n+ Isub n+ IPT IGIDL ID P - bulk nMOS Transistor P.K. Shetty, MSIS, MAHE 29 Leakage Current Components 1. Subthreshold leakage, Isub 2. Reverse bias pn junction leakage, ID 3. Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap 4. Drain source punch-through, IPT due to short channel and high drain-source voltage 5. Gate tunneling, IG through thin oxide; may become significant with scaling. P.K. Shetty, MSIS, MAHE 1. Subthreshold Leakage, Isub  Occurs when VGS < VTH (weak inversion), where minority carrier concentration is small, but not zero.  Subthreshold conduction is dominated by the diffusion current  This leakage component is the dominant modern device OFF-state leakage due to the low VTH that is used. P.K. Shetty, MSIS, MAHE 31  Subthreshold Leakage, Isub a) For Long Channel Devices: Isub = μ0 Cox (W/L) vT2 exp {(VGS –VTH ) / vT } μ0: zero bias carrier surface mobility Cox: gate oxide capacitance per unit area L: channel length W: gate width vT = kT/q: thermal voltage : a technology parameter P.K. Shetty, MSIS, MAHE 32 Where, Poly SiO2 Channel dep P-sub P.K. Shetty, MSIS, MAHE 33  b) For Short Channel Devices: Isub= μ0 Cox(W/L)vT2 exp{(VGS –VTH + nVDS)/ηvT} VDS = drain to source voltage n: a DIBL constant W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp. 81-104 P.K. Shetty, MSIS, MAHE 34