COMPE572 VLSI Circuit Design Lectures Fall 2024 PDF

COMPE 572 VLSI CIRCUIT DESIGN Week 1 Instructor: Zdravko Lukic ([email protected]) Fall 2024 Real-Life Motivation for COMPE572 (1) Source: https://unitedlex.com/insights/apple-iphone-14-pro-teardown-report/...

COMPE 572 VLSI CIRCUIT DESIGN Week 1 Instructor: Zdravko Lukic ([email protected]) Fall 2024 Real-Life Motivation for COMPE572 (1) Source: https://unitedlex.com/insights/apple-iphone-14-pro-teardown-report/ 2 Real-Life Motivation for COMPE572 (2) Source: https://unitedlex.com/insights/apple-iphone-14-pro-teardown-report/ 3 Real-Life Motivation for COMPE572 (3) Source: https://unitedlex.com/insights/apple-iphone-14-pro-teardown-report/ 4 COMPE 572 High-Level Course Objectives The course covers design of digital integrated circuits based on CMOS technology; characterization of field effect transistors, transistor level design and simulation of logic gates and subsystems; chip layout, design rules, introduction to processing; ALU architecture. The course focuses on three major technical areas: 1. VLSI circuit design and analysis of mixed signal, analog/digital, electronic systems. 2. VLSI chip design and subsystem integration (circuit & layout level) 3. VLSI circuit test, verification and post-si validation. The course involves Cadence Virtuoso Analog Design Environment for circuit design simulations, schematic entry, and chip layout. Matlab / Simulink is also used for the class projects and reports. Download instruction➔ https://library.sdsu.edu/computers-technology/software/matlab 5 Compe 572 Course Enrollment Info Adding /Dropping must be done through SDSU WebPortal before Sept 09. Course foundation: COMPE 271 Computer Organization. EE330 Fundamentals of Engineering Electronics. 6 COMPE572 Focus and Key Milestones Date Activity Assignment Week 1 Introduction. CMOS transistor. CMOS Logic Design. Layout. Week 2 CMOS Transistor Theory and Applications. Week 3 CMOS Processing Technology Quiz 1, Project 1 Week 4 CMOS Circuit Delays Week 5 CMOS Circuit Power Quiz 2 Week 6 CMOS Interconnect & Robustness Project 2 Week 7 CMOS Combinatorial Circuit Design Quiz 3 Week 8 CMOS Sequential Circuit Design Week 9 CMOS Datapath Systems Midterm Week 10 CMOS Memory Circuits Project 3 Week 11 CMOS Special-Purpose Circuits (PLLs, IOs, Random Circuits). Quiz 4, Week 12 CMOS Design Methodology and Tools Project 4 Week 13 CMOS Testing and Debugging Quiz 5 Week 14 CMOS Verification. Week 15 Final Project Presentations and Exam Review Quiz 6 12/17/2024 Final Exam 7 COMPE572 Grading Breakdown (1/2) Quizzes (15% of total grade) 6 closed-book/closed-note quizzes. The best five grades will be counted – 3% each (15% total). Ungraded homework problems will be assigned to prepare you with the quizzes. Midterm (20% of total grade) Tue, October 22, 11:00AM to 12:15PM (in class). Closed-book/closed-notes. 1-page handwritten cheat sheet you prepared is allowed. Cheat sheet with useful formulas. You are required to bring a calculator. 8 COMPE572 Grading Breakdown (2/2) Projects (35% of total grade) 4 projects @ 8.75% each will be assigned. You will work in pairs for all projects. The grading will be performed based on a project report and/or presentation for each project. The report and/or presentation should describe: Design procedure. How well simulation results match the target design criteria? Reasons for any significant discrepancy from the target specs (>10%). Summary of challenges that are addressed. For projects, you will use Cadence Virtuoso software and Matlab. Final (30% of total grade) Tue , Dec 17, 10:30AM-12:30PM. Closed-book/closed-notes. 1-page handwritten cheat sheet you prepared is allowed. Cheat sheet with useful formulas. You are required to bring a calculator. 9 COMPE572 Class Policies and Procedures Cheating on quizzes, midterms, assignments, or the final will be punished by a zero grade on that item and possibly an automatic “F” for the course. The University adheres to a strict policy regarding cheating-and- plagiarism. These activities will not be tolerated in this class. Become familiar with the policy and what constitutes plagiarism. Any cheating or plagiarism will result in failing this class and a disciplinary review by the University. These actions may lead to probation, suspension, or expulsion. 10 COMPE572 Book 11 Tips for success with COMPE572 To get successful in the class: Attend all lectures and complete homework assignments. Go over the lecture material before and after the lecture. Ask anything that is not clear. Attend the office hours → T/TH 12:15-13:00. When studying for the quizzes and tests, attempt all questions first by yourself, then go over the solutions. 12 Interaction with Instructor Office hours @E-403H : Tuesday-Thursday 12:15PM-1:00PM. 12:30PM deadline to show up for consultations (unless a student notifies the instructor about the later arrival). Emails: [email protected] 13  Introduction ❑ Integrated circuits: many transistors on one chip. ❑ Very Large Scale Integration (VLSI): bucketloads! ❑ Complementary Metal Oxide Semiconductor – Fast, cheap, low power transistors ❑ Today: How to build your own simple CMOS chip – CMOS transistors – Building logic gates from transistors – Transistor layout and fabrication ❑ Rest of the course: How to build a good CMOS chip 0: Introduction CMOS VLSI Design 4th Ed. 14  Silicon Lattice ❑ Transistors are built on a silicon substrate ❑ Silicon is a Group IV material ❑ Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si 0: Introduction CMOS VLSI Design 4th Ed. 15  Dopants ❑ Silicon is a semiconductor ❑ Pure silicon has no free carriers and conducts poorly ❑ Adding dopants increases the conductivity ❑ Group V: extra electron (n-type) ❑ Group III: missing electron, called hole (p-type) Si Si Si Si Si Si - + + - Si As Si Si B Si Si Si Si Si Si Si 0: Introduction CMOS VLSI Design 4th Ed. 16  p-n Junctions ❑ A junction between p-type and n-type semiconductor forms a diode. ❑ Current flows only in one direction p-type n-type anode cathode 0: Introduction CMOS VLSI Design 4th Ed. 17  nMOS Transistor ❑ Four terminals: gate, source, drain, body ❑ Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor Source Gate Drain Polysilicon – Even though gate is SiO2 no longer made of metal* n+ n+ Body p bulk Si * Metal gates are returning today! 0: Introduction CMOS VLSI Design 4th Ed. 18  nMOS Operation ❑ Body is usually tied to ground (0 V) ❑ When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF Source Gate Drain Polysilicon SiO2 0 n+ n+ S D p bulk Si 0: Introduction CMOS VLSI Design 4th Ed. 19  nMOS Operation Cont. ❑ When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO2 1 n+ n+ S D p bulk Si 0: Introduction CMOS VLSI Design 4th Ed. 20  pMOS Transistor ❑ Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si 0: Introduction CMOS VLSI Design 4th Ed. 21  Power Supply Voltage ❑ GND = 0 V ❑ In 1980’s, VDD = 5V ❑ VDD has decreased in modern processes – High VDD would damage modern tiny transistors – Lower VDD saves power ❑ VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … 0: Introduction CMOS VLSI Design 4th Ed. 22  Transistors as Switches ❑ We can view MOS transistors as electrically controlled switches ❑ Voltage at gate controls path from source to drain g=0 g=1 d d d nMOS g OFF ON s s s d d d pMOS g OFF ON s s s 0: Introduction CMOS VLSI Design 4th Ed. 23  CMOS Inverter A Y VDD 0 1 1 0 OFF ON 0 1 A Y ON OFF A Y GND 0: Introduction CMOS VLSI Design 4th Ed. 24  CMOS NAND Gate A B Y 0 0 1 ON OFF OFF ON OFF ON 0 1 1 1 Y 1 0 1 0 ON A OFF 1 1 0 0 1 1 0 OFF ON B ON OFF 0: Introduction CMOS VLSI Design 4th Ed. 25  CMOS NOR Gate A B Y 0 0 1 A 0 1 0 1 0 0 B 1 1 0 Y 0: Introduction CMOS VLSI Design 4th Ed. 26  3-input NAND Gate ❑ Y pulls low if ALL inputs are 1 ❑ Y pulls high if ANY input is 0 Y A B C 0: Introduction CMOS VLSI Design 4th Ed. 27  CMOS Fabrication ❑ CMOS transistors are fabricated on silicon wafer ❑ Lithography process similar to printing press ❑ On each step, different materials are deposited or etched ❑ Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process 0: Introduction CMOS VLSI Design 4th Ed. 28  Inverter Cross-section ❑ Typically use p-type substrate for nMOS transistors ❑ Requires n-well for body of pMOS transistors A GND VDD Y SiO2 n+ diffusion p+ diffusion n+ n+ p+ p+ polysilicon n well p substrate metal1 nMOS transistor pMOS transistor 0: Introduction CMOS VLSI Design 4th Ed. 29 Well and Substrate Taps ❑ Substrate must be tied to GND and n-well to VDD ❑ Metal to lightly-doped semiconductor forms poor connection called Shottky Diode ❑ Use heavily doped well and substrate contacts / taps A GND VDD Y p+ n+ n+ p+ p+ n+ n well p substrate well substrate tap tap 0: Introduction CMOS VLSI Design 4th Ed. 30  Inverter Mask Set ❑ Transistors and wires are defined by masks ❑ Cross-section taken along dashed line A Y GND VDD nMOS transistor pMOS transistor substrate tap well tap 0: Introduction CMOS VLSI Design 4th Ed. 31  Detailed Mask Views ❑ Six masks n well – n-well – Polysilicon Polysilicon – n+ diffusion – p+ diffusion n+ Diffusion – Contact p+ Diffusion – Metal Contact Metal 0: Introduction CMOS VLSI Design 4th Ed. 32  Fabrication ❑ Chips are built in huge factories called fabs ❑ Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted. 0: Introduction CMOS VLSI Design 4th Ed. 33  Fabrication Steps ❑ Start with blank wafer ❑ Build inverter from the bottom up ❑ First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 34  Oxidation ❑ Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 35  Photoresist ❑ Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light Photoresist SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 36  Lithography ❑ Expose photoresist through n-well mask ❑ Strip off exposed photoresist Photoresist SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 37  Etch ❑ Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! ❑ Only attacks oxide where resist has been exposed Photoresist SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 38  Strip Photoresist ❑ Strip off remaining photoresist – Use mixture of acids called piranah etch ❑ Necessary so resist doesn’t melt in next step SiO2 p substrate 0: Introduction CMOS VLSI Design 4th Ed. 39  n-well ❑ n-well is formed with diffusion or ion implantation ❑ Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si ❑ Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si SiO2 n well 0: Introduction CMOS VLSI Design 4th Ed. 40  Strip Oxide ❑ Strip off the remaining oxide using HF ❑ Back to bare wafer with n-well ❑ Subsequent steps involve similar series of steps n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 41  Polysilicon ❑ Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers) ❑ Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor Polysilicon Thin gate oxide n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 42  Polysilicon Patterning ❑ Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 43  Self-Aligned Process ❑ Use oxide and masking to expose where n+ dopants should be diffused or implanted ❑ N-diffusion forms nMOS source, drain, and n-well contact n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 44  N-diffusion ❑ Pattern oxide and form n+ regions ❑ Self-aligned process where gate blocks diffusion ❑ Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing n+ Diffusion n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 45  N-diffusion cont. ❑ Historically dopants were diffused ❑ Usually ion implantation today ❑ But regions are still called diffusion n+ n+ n+ n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 46  N-diffusion cont. ❑ Strip off oxide to complete patterning step n+ n+ n+ n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 47  P-Diffusion ❑ Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 48  Contacts ❑ Now we need to wire together the devices ❑ Cover chip with thick field oxide ❑ Etch oxide where contact cuts are needed Contact Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 49  Metalization ❑ Sputter on aluminum over whole wafer ❑ Pattern to remove excess metal, leaving wires Metal Metal Thick field oxide p+ n+ n+ p+ p+ n+ n well p substrate 0: Introduction CMOS VLSI Design 4th Ed. 50  Layout ❑ Chips are specified with set of masks ❑ Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) ❑ Feature size f = distance between source and drain – Set by minimum width of polysilicon ❑ Feature size improves 30% every 3 years or so ❑ Normalize for feature size when describing design rules ❑ Express rules in terms of  = f/2 – E.g.  = 0.3 m in 0.6 m process 0: Introduction CMOS VLSI Design 4th Ed. 51  Simplified Design Rules ❑ Conservative rules to get you started 0: Introduction CMOS VLSI Design 4th Ed. 52  Inverter Layout ❑ Transistor dimensions specified as Width / Length – Minimum size is 4 / 2 sometimes called 1 unit – In f = 0.6 m process, this is 1.2 m wide, 0.6 m long 0: Introduction CMOS VLSI Design 4th Ed. 53  Summary ❑ MOS transistors are stacks of gate, oxide, silicon ❑ Act as electrically controlled switches ❑ Build logic gates out of switches ❑ Draw masks to specify layout of transistors ❑ Now you know everything necessary to start designing schematics and layout for a simple chip! 0: Introduction CMOS VLSI Design 4th Ed. 54 References Chapter 1 : David Money Harris Neil H. E. Weste, CMOS VLSI Design 4e: A circuits and systems perspective, 4th edition, Pearson, 2010. ISBN: 978-9332542884 Portion of the lecture notes used the textbook note material by David Money Harris (textbook author). 55