EGEC4220 Linear Integrated Circuits PDF

EGEC4220 Linear Integrated Circuits Learning Outcome 1 Illustrate the manufacturing process of Integrated Circuits (ICs)  EGEC4220 - Linear Integrated Circuits...

EGEC4220 Linear Integrated Circuits Learning Outcome 1 Illustrate the manufacturing process of Integrated Circuits (ICs)  EGEC4220 - Linear Integrated Circuits Course Level: Course Name: Linear Integrated Circuits Credit hours: 3 Academic Year: 2024-25 BTech Contact Theory (hr/week): 2 Semester: ☐ Fall Hours: Passing Grade: Course Code: EGEC4220 ☒ Spring C / 67 Practical (hr/week): 2 ☐ Summer Course Type: (Tick all that applies) ☐ University Requirement ☐ College Requirement Course Pre-requisite(s)/ Co-requisite(s): EGEC3110 ☐ University Elective ☒ Specialization Requirement Electronics II ☐ Department Requirement ☐ Specialization Elective ☐ Department Elective Section Day(s) Time Location SUN 12 - 02PM SA303 Schedule 1 of Course THU 12 - 02PM EE102 Lectures MON 02 - 04PM SA303 2 WED 02 - 04PM EE102 EGEC4220 - Linear Integrated Circuits  EGEC4220 - Linear Integrated Circuits Assessment Plan No. Assessment Activity Weight % Learning Outcomes Mapping 1 Quiz total (Mandatory 2 Quizzes) 10 3&5 2 Attendance, and HSE 5 1-7 3 Aim / Objectives, Procedure, Table, Graphs, & Results 10 2-6 4 Lab Test 10 2-6 5 Case Study 10 7 6 Midterm Exam (1 Hour) 20 1,2,3 & 4 part 7 Final Exam (2 Hours) 35 1-7 Total 100 1-7 TEXT BOOK: EGEC4220 - Linear Integrated Circuits R. L. Boylestad and L. Nashelsky, Electronic Devices and Circuit Theory, New Jersey: Pearson Education, Inc., 2013. A. Malvino and D. Bates, Electronic Principles, New York: McGraw-Hill Education, 2016. T. L. Floyd, Electronic Devices, New Jersey: Pearson Education, Inc., 2012. D. Roy Choudhry and Shail B. Jain, "Linear Integrated Circuits"- (d/e), New Age International Pvt. Ltd, 2011 R. A. Gayakwad, Op-Amps and Linear Integrated Circuits, New Jersey: Pearson Education, Inc., 2001. REFERENCE BOOKS: Bakshi, Uday A / Godse, Atul P, Linear Integrated Circuits & Applications, 1st Ed., Technical Publications, 2011. ISBN- 9788189411305. Dudeja, Ravi Raj / Duckworth, R James, Op-Amps And Linear Integrated Circuits, 1st Ed, Umeshpublication, 2002AmpsAnd Linear Integrated Circuits Masader Website: https://www.masader. om/  EGEC4220 - Linear Integrated Circuits OUTLINE 1. Introduction 2. Why Silicon 3. The purity of Silicon 4. Classification of IC 5. Scale of Integration 6. Types of Integrated Circuits 7. Advantage & Disadvantages of IC 8. Steps Involved in IC Fabrication  INTRODUCTION: In the world of semiconductor devices and integrated circuits, silicon is one of the commonly used semiconductor material, and it is mostly used as a substrate material. For example, solar cells made of silicon wafers are cheaper and can be used for practical applications by common people. Today compound semiconductors are the main point of attraction. IV–IV, III–V and II–VI are the common compound semiconductors used in research and industry. Among these the compound semiconductor III–V is widely used as it has multiple applications in LED, LASER, etc. gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP) and gallium nitride (GaN) and aluminum nitride (AlN)—are the III–V compound which are widely used. Most of the Optoelectronic devices uses III–V compound. The microminiaturization of electronics circuits and systems and then concomitant (naturally accompanying or associated) application to computers and communications represent major innovations of the twentieth century. These have led to the introduction of new applications that were not possible with discrete devices. Integrated circuits on a single silicon wafer followed by the increase of the size of the wafer to accommodate many more such circuits served to significantly reduce the costs while increasing the reliability of these circuits. WHY SILICON? Semiconductor devices are of two forms (i) Discrete Units (i) Integrated Units Discrete Units can be diodes, transistors, etc. Integrated Circuits uses these discrete units to make one device. Integrated Circuits can be of two forms (i) Monolithic-where transistors, diodes, resistors are fabricated and interconnected on the same chip. (ii)Hybrid- in these circuits, elements are discrete form, and others are connected on the chip with discrete elements externally to those formed on the chip ❑ Two other semiconductors, germanium and gallium arsenide, present special problems while silicon has certain specific advantages not available with the others. ❑ A major advantage of silicon, in addition to its abundant (available in large quantities) availability in the form of sand, is that it is possible to form a superior stable oxide, SiO2, which has superb insulating properties. ❑ Gallium arsenide crystals have a high density of crystal defects, which limit the performance of devices made from it. ❑ Compound semiconductors, such as GaAs (in contrast to elemental semiconductors such as Si and Ge) are much more difficult to grow in single crystal form. ❑ Both Si and Ge do not suffer, in the processing steps, from possible decomposition that may occur in compound semiconductors such as GaAs. ❑ Lastly, at the present time, silicon remains the major semiconductor in the industry.  THE PURITY OF SILICON The starting form of silicon, which manufacturers of devices and integrated circuits use, is a circular slice known as a wafer. These wafer diameters vary from 10-20 cms with maximum up to 30 cms. Silicon is found in abundance(extremely large) in nature as an oxide in sand and quartz. Silicon must be in Crystalline form Very pure, Free of defects and Uncontaminated. Classification of Integrated Circuits IC’s are classified based on (i) Scale of Integration (ii) Types of Signal (iii) Types of fabrication Techniques SCALE OF INTEGRATION: Historically, the first semiconductor IC chip held one diode/transistor. Advancement of technology enabled to add more and more transistors. The first to arrive was small-scale integration (SSI), then improvements in technique led to devices with hundreds of logic gates—large-scale integration (LSI). TYPES OF INTEGRATED CIRCUITS: 1. Monolithic IC: In the Monolithic IC the entire circuit is built into a single piece of semiconductor chip, which consists of active and passive components. The most commonly used integrated circuits are, microprocessor ICs, memory ICs, etc., and all are examples of monolithic ICs. 2. Hybrid IC: In Hybrid IC the electronic circuit is generally integrated in the ceramic substrate using various components and then enclosed in the single package. The hybrid IC consists of several monolithic ICs connected by metallic interconnects mounted on a common substrate. Hybrid IC technology bonds various substrates either at the die level or at the wafer level. This technology streamlines the connections between different semiconductor chips by replacing wire bonding. This process achieves an accelerated, streamlined and less costly process. Hybrid IC allows increase in communication bandwidth and facilitates higher system yield. ADVANTAGES AND DISADVANTAGES OF IC: The advantages of integrated circuits are as follows: 1. Small in size due to the reduced device dimension 2. Low weight due to very small size 3. Low power requirement due to lower dimension and lower threshold power requirement 4. Low cost due to large-scale production 5. High reliability due to the absence of a solder joint 6. Facilitates integration of large number of devices 7. Improves the device performance even at high-frequency region The disadvantages of integrated circuits are as follows: 1. IC resistors have a limited range 2. Generally inductors (L) cannot be formed using IC 3. Transformers cannot be formed using IC  Silicon From Sand ? https://youtu.be/JDROPMoNZpk?si=Lo1ImEEy-64BYy9_ https://youtu.be/Bu52CE55BN0?si=5r7b106SuP2MPCKH STEPS INVOLVED IN IC FABRICATION 1. Silicon wafer (substrate) preparation 2. Epitaxial growth 3. Oxidation 4. Photolithography 5. Diffusion 6. Ion implantation 7. Isolation technique 8. Metallization 9. Assembly processing & packaging 1. CRYSTAL GROWTH AND WAFER PREPARATION: The Czochralski Process ❑To grow crystals, one starts with very pure semiconductor grade silicon, which is melted in a quartz-lined graphite crucible. The melt is held at a temperature of 1690K, which is slightly greater than the melting point (1685K) of silicon. (°C = K - 273.15) Seed Crystal After having set up the melt, a seed crystal (a small highly perfect crystal), attached to a holder and possessing the desired crystal orientation, is dipped into the melt and a small portion is allowed to melt. https://youtu.be/TMKsYJmzOG4?si=x4b2o5q1jXQu_hLs  Crystal growth and wafer preparation is the most fundamental step in device fabrication. Various crystal growth techniques are used to form the bulk crystal. One of the methods is the Czochralski process. A small seed crystal of silicon is attached to the top of a rod and lowered into a crucible of molten silicon to which acceptor impurities have been added. As the rod is very slowly pulled out of the ‘melt’ under carefully controlled conditions, we find that a single p-type or n-type crystal ingot of the order of several inches has grown. The ingot is subsequently sliced into round wafers to form the substrate on which all integrated components are fabricated. One side of each wafer is lapped and polished to eliminate surface imperfections before proceeding with the next process. Here is a picture of a state-of-the-art 200 mm Si crystal as they are grown by the thousands for present day (2000) chip manufacture.  Ingot Slicing and Wafer Preparation ❑ In the final process, when the bulk of the melt has been grown, the crystal diameter is decreased until there is a point contact with the melt. ❑ The resulting ingot is cooled and removed to be made into wafers. The ingots have diameters as large as 200mm, with latest ones approaching 300mm. The ingot length is of the order of 100cm. ❑Slicing the wafers to be used in the fabrication of integrated circuits is a procedure that requires precision equipment. ❑The object is to produce slices that are perfectly flat and as smooth as possible, with no damage to the crystal structure. ❑The wafers need to be subjected to a number of steps known as lapping, polishing, and chemical etching. ❑The wafers are cleaned, rinsed, and dried for use in the fabrication of discrete devices and integrated circuits  2. EPITAXIAL GROWTH Epitaxial growth technology uses the hydrogen reduction of gases like silane (SiH4) or silicon tetrachloride (SiCl4) as the source for the silicon to be grown. Silane has two advantages. It requires a lower temperature and has a faster growth rate than silicon tetrachloride. The chemical reaction for the hydrogen reduction of SiCl4 is: 1200 0C SiCl4 + 2H2 Si + 4HCl And that for SiH4 is: H2 atmosphere, 10000C SiH4 Si +2H2 For example, an n-type epitaxial layer, typically from few nanometre to few micrometre thick, is grown into a p-type substrate having resistivity of approximately few cm. Since epitaxial growth requires the production of epitaxial films of impurity concentrations, it is essential to introduce impurities, such as Phosphine (PH3) for n-type doping or Diborane (B2H6) for p-type doping into the silicon substrate.  Epitaxy is used to deposit N on N+ silicon, which is impossible to accomplish by diffusion. Epitaxy is also used in isolation between bipolar transistors wherein N- is deposited on Phosphorus(P). The list below, and with reference to Figure, the sequence of operation involved in the process: 1. Heat wafer to 1200°C. 2. Turn on H2 to reduce the SiO2 on the wafer surface. 3. Turn on anhydrous(no water) HCl(Hydrogen Chloride) to vapor- etch the surface of the wafer. This removes a small amount of silicon and other contaminants. 4. Turn off HCl. 5. Drop temperature to 1100°C. 6. Turn on silicon tetrachloride (SiCl4). 7. Introduce dopant. Class Activity 1. The purification process of Silicon involves the reaction of Silicon Tetrachloride vapor (SiCl4(g)) with hydrogen to 1250oC to form solid Silicon and Hydrogen Chloride. (a) Write a balanced equation for this reaction. (b) What is being oxidized, and what is being reduced? (c) Which substance is the reductant, and which is the oxidant? Class Activity 1. The purification process of Silicon involves the reaction of Silicon Tetrachloride vapor (SiCl4(g)) with hydrogen to 1250oC to form solid Silicon and Hydrogen Chloride. (a) Write a balanced equation for this reaction. (b) What is being oxidized, and what is being reduced? (c) Which substance is the reductant, and which is the oxidant? Redox = Reduction + Oxidation (Reduction – gain e-s & Oxidation – Loose e-s) +4 -1 0 1250 0 +1 -1 (a) SiCl4(g) + 2 H2 → Si (s) + 4 HCl(g) (b) Si + 4e- → Si (s) - Reduction H2 → 2 H + 2 e- | 2 times - Oxidation (c) H2 → Reductant ( gives electrons; forces Si to be reduced) SiCl4 → Oxidant  3. OXIDATION FOR ISOLATION: Silicon technology has the natural ability to grow an oxide layer on the SiO2 layer. As a passivating layer SiO2 has the following characteristics: 1.The impurities that are used to dope the silicon do not penetrate n-type Si wafer. Thus, when used with the masking techniques, selective doping of specific regions of the chip is accomplished. 2. It is capable of being etched by hydrogen fluoride (HF). Thermal oxidation of silicon is achieved in the presence of water vapour; this process is called wet oxidation. The chemical reaction for this process is: Si + 2H2O → SiO2 + 2H2 Wet oxidation is an oxidative pretreatment method that consists of the addition of water and an oxidizing agent (e.g. air, oxygen, and hydrogen peroxide [H2O2]) to feedstocks(raw material) prior to pretreatment. The temperature, reaction time, oxygen pressure, and water content are the most critical parameters in wet oxidation. Dry oxidation of oxygen: Si + O2 → SiO2 The thickness of the oxide layers is generally in the order of 0.02 mm to 2 mm. Process temperature, impurity concentration, and processing time are several of the factors that influence the thickness of the SiO2 layer. Thermal oxidation is a way to produce a thin layer of oxide on the surface of a material. Thermal oxide (silicon dioxide) is a silicon dioxide film produced by the oxidation of substrate silicon, usually at temperatures in excess of 1000°C. Silicon dioxideplays an important role in shielding of the surface so that dopant atoms, by diffusion or ion implantation, may be driven into other selected regions 4. PHOTOLITHOGRAPHY 1. The wafer is baked at 100°C to solidify the resist on the wafer. 2. The reticle is placed on the wafer and aligned by computer control. 3. The reticle is exposed to ultraviolet light with the transparent parts of the reticle passing the light onto the wafer. The photoresist under the opaque regions of the reticle is unaffected. 4. The exposed photoresist is chemically removed by dissolving it in an organic solvent and exposing the silicon dioxide underneath. This is a process very similar to that used in developing photographic film. The exposed silicon dioxide is then etched away using hydrofluoric acid, which dissolves silicon dioxide and not silicon. The regions under the opaque part of the reticle are still covered by the silicon dioxide and the photoresist. The photoresist under the opaque regions of the reticle is stripped using a proper solvent and the silicon dioxide is exposed. Etching Techniques Etching is the process of selective removal of regions of a semiconductor, metal, or silicon dioxide. There are two types of etchings: wet and dry In wet etching, the wafers are immersed in a chemical solution at a predetermined temperature. In this process, the material to be etched is removed equally in all directions so that some material is etched from regions where it is to be left. This becomes a serious problem when dealing with small dimensions. In dry (or plasma) etching, the wafers are immersed in a gaseous plasma created by a radio-frequency electric field applied to a gas such as argon. Electrons are initially released by field emission from an electrode. These electrodes gain kinetic energy from the field, collide with, and transfer energy to the gas molecules, which results in generating ions and electrons. The newly generated electrons collide with other gas molecules and the avalanche process continues throughout the gas, forming a plasma. The wafer to be etched is placed on an electrode and is subjected to the bombardment of its surface by gas ions. As a result, atoms at or near the surface to be etched are removed by the transfer of momentum from the ions to the atoms. 5. Diffusion Most of these diffusion processes occur in two steps: the predeposition and the drive-in diffusion. In the pre deposition step, a high concentration of dopant atoms are introduced at the silicon surface by a vapor that contains the dopant at a temperature of about 1000°C. In recent years Ion Implantation is used. At the temperature of l000°C,silicon atoms move out of their lattice sites creating a high density of vacancies and breaking the bond with the neighboring atoms. The second step is drive in process, used to drive the impurities deeper into the surface without adding anymore impurities. Common dopants are boron for P-type layers and phosphorus, antimony, and arsenic for N-type layers. A typical arrangement of the process of diffusion is shown in Figure. The wafers are placed in a quartz furnace tube that is heated by resistance heaters surrounding it. So that the wafers may be inserted and removed easily from the furnace, they are placed in a slotted quartz carrier known as a boat. To introduce a phosphorus dopant, as an example, phosphorus oxychloride 6. Ion Implantation To generate ions, such as those of phosphorus, an arc discharge is made to occur in a gas, such as phosphine (PH3),that contains the dopant. The ions are then accelerated in an electric field so that they acquire an energy of about 20keV and are passed through a strong magnetic field. Because during the arc discharge unwanted impurities may have been generated, the magnetic field acts to separate these impurities from the dopant ions based on the fact that the amount of deflection of a particle in a magnetic field depends on its mass. Following the action of the magnetic field, the ions are further accelerated so that their energy reaches several hundred keV, whereupon they are focused on and strike the surface of the silicon wafer. Advantages of Ion Implantation 1. Doping levels can be precisely controlled since the incident ion beam can be accurately measured as an electric current 2. The depth of the dopant can be easily regulated by control of the incident ion velocity. It is capable of very shallow penetrations. 3. Extreme purity of the dopant is guaranteed. 4. The doping uniformity across the surface can be accurately controlled. 5. Because the ions enter the solid as a directed beam, there is very little spread of the beam, thus the doping area can be clearly defined. 6. Since this is a low-temperature process, the movement of impurities is minimized. 7. Isolation Techniques ❑ In IC it is necessary to provide electrical isolation between different components and interconnections. ❑ The two commonly used techniques are p-n junction isolation and dielectric isolation. P-N JUNCTION ISOLATION: In this p type impurities are diffused into n type epitaxial layer. ❑ In dielectric isolation, a layer of solid dielectric such as SiO2 or ruby completely surrounds each components thereby producing isolation, both electrical and physical. ❑ This isolating dielectric layer is thick enough so that its associated capacitance is negligible. Also, it is possible to fabricate both PNP and NPN transistors within the same silicon substrate. 8. Metallization for interconnection ❑ The process of producing a thin metal film layer that will serve to make interconnection of the various components on the chip is called metallization. ❑ Metallization takes place towards the end of the fabrication process and involves the deposition of a thin layer of aluminium over the whole of the wafer and then the use of photolithography to define the interconnect pattern. ❑ Aluminium is preferred for metallization. ▪ It is a good conductor. ▪ It makes good mechanical bonds with silicon. ▪ It forms a low resistance contact. ▪ It can be applied and patterned with a single deposition and etching process. 4" Wafer after Metallization  Testing for Reliability After all the fabrication processes are done successfully, the semiconductor device is tested thoroughly through the different, characterization processes. IC’s are fabricated by the batch process so some of the IC may not perform according to standard. An electronic tester presses tiny probes against the chip to check its functional property. 9. Assembly processing & packaging Each of the wafer processed contains several hundred chips. So these chips are separated and packaged by a method called scribing and cleaving. This method uses a diamond tipped tool to cut lines along the rectangular grid separating the individual chips. There are three package configurations available they are metal can package, ceramic flat package, dual in line package.  The last step of this process is packaging. Packaging is done according to the dimension of the product type, and the requirements of the manufacturer. The wafer is certified then the wafer is broken into small individual dies. Small wires are bonded to connect pads to the external connection pins. The most common packaging is dual input packaging or DIP, mostly used in digital IC. Planar Resistance Fabrication Process Description 1. An N+ substrate grown by the Czochralski process is the starting metal of approximately 150μm thick. 2. A layer of N-type silicon (1-5μm) is grown on the substrate by epitaxy. 3. Silicon dioxide layer deposited by oxidation. 4. Surface is coated with photoresist (positive). 5. Mask is placed on surface of silicon, aligned, and exposed to UV light. 6. Mask is removed, resist is removed, and SiO2 under the exposed resist is etched. 7. Boron is diffused to form P region. Boron diffuses easily in silicon but not in SiO2 8. Thin aluminum film is deposited over surface. 9. Metallized area is covered with resist and another mask is used to identify areas where metal is to be preserved. Wafer is etched to remove unwanted metal. Resist is then dissolved. 10. Contact metal is deposited on the back surface and ohmic contacts are made by heat treatment. Planar PN Junction Diode Fabrication Homework Fabrication Steps for Different Circuits 1. Capacitor 2. Transistor  POINTS TO REMEMBER: 1. In monolithic circuits, the entire circuit is built into a single piece of semiconductor chip consisting of passive and active components; physical properties of the semiconductor determine performance of the circuit. 2. Hybrid integrated circuits are devices that apply standard semiconductor processing technology to individual ICs, and fuse them together to simultaneously form an electrical, mechanical, and thermal bond. 3. Hybrid integrated circuit offers a new a paradigm in integrated circuit and system designs and architectures by permitting: (a) Increase in communication bandwidth (b) Modular chip design process (c) Higher system yields with more reliability 4. Integrated circuits have the following advantages: (a) Small in size due to the reduced device dimension (b) Low weight due to very small size (c) Low power requirement due to lower dimension and lower threshold power requirement (d) Low cost due to large-scale production 5. The Czochralski process is used to grow ingot and subsequently to design the wafer.  POINTS TO REMEMBER: 6. The epitaxial process is used to form a layer of single-crystal silicon on an existing crystal wafer of the same or different material. 7. Thermal oxidation of silicon is achieved in the presence of water vapour; this process is called wet oxidation. 8. The process for pattern definition by applying thin uniform layer of viscous liquid photo resist on the wafer surface is the photolithography process. 9. The composite drawing of the circuit is partitioned into several levels called masking levels, used in fabricating the chip. 10. Etching is the process of removing the unwanted portion of the layer or region from the surface during the fabrication process. Etching can be of two types: (a) Dry etching (b) Chemical etching 11. Diffusion of impurities into substrate layer is the basic step in the planar process. 12. The ionized particles are accelerated through an electrical field and targeted at the semiconductor Wafer. 13. The metallization process is used to form the interconnections of the components on the chip. 14. IC testing is performed before packaging.