Microprocessor Systems Lecture Notes PDF

IT2020 Intro to Microprocessor Systems A microprocessor has the capability of executing instructions at an extremely high speed. It has five basic components arithmetic logic unit (ALU), control unit (CU), registers, buses, and timing unit. Microprocessor Architecture Classification - Instruction...

IT2020 Intro to Microprocessor Systems A microprocessor has the capability of executing instructions at an extremely high speed. It has five basic components arithmetic logic unit (ALU), control unit (CU), registers, buses, and timing unit. Microprocessor Architecture Classification - Instruction Set Architecture Complexity-Based Classification (Measure based on the complexity of instructions) o Complex instruction set computers (CISC) ▪ One of the advantages of CISC architecture is performing multiple operations in a single complex instruction. However, complex instructions require many processor clock cycles to complete, wherein most of the instructions can access the memory. o Reduced Instruction Set Computers (RISC) ▪ This architecture is suited for those scenarios wherein the processor speed-matches memories. This speed-matching reduces the penalty for instruction or parameter fetching from the memory. Instruction Operand-Based Classification - Instructions in an assembly language program have multiple operand types. o Memory-memory: This type of ISA allows more than one operand of most instructions to be specified in memory. o Register-memory: This allows one operand of an instruction to be specified in memory, while the other operand is in the CPU register. o Register-register: This is also called load-store architecture. Direct access to the memory is not allowed to most of the instructions in this ISA. Microprocessor Architecture Classification - Memory Interface-Based Architecture The von Neumann architecture uses a common bus for both data as well as code memory. As a result, either an instruction can be fetched from memory, or data can be read from or written to the memory during each memory access cycle. The Harvard architecture utilizes separate buses for accessing code and data memories. Using separate buses for code and data memories allows instructions and data to be accessed simultaneously. Software Sub-Systems Operating System (OS) o OS is in-charge of a collection of resources, including the microprocessor, memory, I/O devices. o OS manages these resources using the hardware architecture-dependent OS components. Device drives or drivers – It allows the operating system to communicate with the hardware devices. Libraries - The software library is a collection of function calls developed for a specific job and is made available to the user. Applications – It is a collection of one or more programs designed to perform operations for a specific application requirement. 01 Handout 1 *Property of STI  [email protected] Page 1 of 4  IT2020 Software Development Tools These are used to convert the user programs to executables, which can be interpreted and run by the microprocessor. Compilation Process o If the user program is written in assembly language, the use of an assembler is needed to convert it to a machine code. o Assembly language programs are also called low-level programs. o If the user program is written in a high-level language, the compiler converts it to the machine code. o The process of converting a user program to machine code using either a compiler or an assembler. Building an Executable Using a Linker o The job of a linker is to construct an executable by combining different object codes obtained after compiling the user program codes or files. o In the process of linking, the linker has to decide what will be the locations (addresses) of different object codes and data segments. o These lists filed can also be used by the tools in debugging: ▪ The use of libraries at the time of building an executable is called static linking. ▪ Libraries that are not used at the time of building an executable, but are used during the execution at runtime, are called dynamic link libraries (DLL). Software-Only Methods Software Simulators – It is a program running on an independent computer hardware platform. It can simulate the execution of the instruction set and the behavior of an I/O of the target microcontroller. Monitors – It is usually residing at the top or bottom region of the microcontroller's memory. It can be used to download to burn the program code in the microcontroller, execute the code, set breakpoints, visualize and modify memory contents or registers. Software-Hardware Debugging Tools Burn and Learn - In many non-complex embedded system developments, the conventional burn and learn method can be used for debugging purposes. o Write or modify the program code. Burn the executable code to the microcontroller chip using a programmer or in-circuit programming capability. Run the program (reset) and learn (observe) for proper functioning. In-Circuit Emulators (ICE) - It is a small hardware tool connected to the targeted microcontroller for in-depth debugging. In-Circuit Debuggers (ICD) - It is a small hardware tool that debugs the targeted microcontroller in Realtime. Bus Architecture A bus is a common pathway through which information flows from one computer component to another. 01 Handout 1 *Property of STI  [email protected] Page 2 of 4  IT2020 These are the common processor bus lines: Data bus – It carries data from one component to another. It is unidirectional for input and output devices and bi-directional for memory and CPU. It is typically a group of wires that connects different components of the computer internally or externally. o Parallel bus - transfers several data bits at the same. These buses typically have 8, 16, 32, or 64 data lines. Ex: ISA, PCI, VESA, and EISA. o Serial bus uses the same line to transfer different data bits of the same byte/word. Typically, they have only one data line with bits being sent one after the other. Ex: USB and IEEE 1394. Control bus – It carries a control signal. The CU uses a control signal for controlling all the components. It is unidirectional from the CPU to all other components. o Bus protocols need to be established for data communication to flow correctly. It may involve characteristics such as the width of the data bus, data transfer size, bus protocols, clocking, etc. ▪ Synchronous Buses - In this bus, its operations are synchronized regarding a clock signal. The bus clock is generally derived from the computer system clock; however, it is often slower than the master clock. ▪ Asynchronous Buses – These buses have no system clock. The process of handshaking is done to properly conduct the transmission of data between the sender and the receiver. o Bus Arbitration - A device that initiates data transfers on the bus at any given time is called a bus master. In a computer system, there may be more than one bus master, such as a DMA controller or a processor. These devices share the system bus. When the current bus master relinquishes, another bus can acquire the control of the processor. ▪ Centralized Arbitration - Only a single hardware device controls the required arbitration, either a processor or an arbiter. Daisy Chaining − It is a simple and cheaper method where all the masters use the same line for making bus requests. Polling Method − In this method, the controller is used to generate address lines for the master. Independent Request − In this scheme, each bus has its bus request and a grant. The built-in priority decoder selects the highest priority requests and asserts the system. ▪ Distributed Arbitration - Each module may claim the bus. All modules have their control logic to manage present buses. Address bus – It carries a memory address. A memory address is a numerical value used for identifying a memory location. o It is used (by the CPU or the DMA-enabled device (direct memory access) to locate the physical address and to communicate read/write commands. o All address busses are read and written by the CPU or DMA in the form of bits. ▪ Ex: A system with a 32-bit address bus can address 4 gibibytes of memory space. Tristate Logic It is a logic used in electronic circuits wherein a third state, the high-impedance state (Hi-Z), is added to the original Logic 1 and Logic 0 states. Aside from the two (2) terminals (namely A and Z), the third terminal (Enable) acts as a selector that blocks out circuits that are not being used. It can be thought of as an input- controlled switch with an output that can be electronically turned “ON” or “OFF” through an external “Control” or “Enable” ( EN ) signal input. 01 Handout 1 *Property of STI  [email protected] Page 3 of 4  IT2020 Characteristics of a Tristate Logic in Computer Buses Tristate Logic is used to allow multiple circuits to share the same output or bus lines, which may not be capable of listening to more than one device or circuit at a time. The processor controls which device has access to the bus by setting the address on the address bus. Only one tristate device can use the bus at any time. The devices not using the bus are disconnected. Their outputs are set to have a high impedance (Hi-Z). Tristate devices respond to a unique address on the address bus. When the main tristate device is disconnected, other devices can share/use the same data bus line. References: Darche, P. (2020). Computer engineering series: Microprocessor 1: Prolegomena – Calculation and storage functions – Models of computation and computer architecture. iSTE & Wiley. Darche, P. (2020). Computer engineering series: Microprocessor 2: Communication in a digital system. iSTE & Wiley. Darche, P. (2020). Computer engineering series: Microprocessor 3: Core Concepts – Hardware Aspects. iSTE & Wiley. de Lamadrid, J. (2018). Computer organization – Basic processor structure. CRC Press. Definition: Address Bus. (n.d.). In Techopedia.com. Retrieved on January 11, 2021, from https://www.techopedia.com/definition/292/address-bus Digital Buffer Tutorial. (n.d.). In Electronics-tutorials.ws. Retrieved on January 11, 2021, from https://www.electronics- tutorials.ws/logic/logic_9.html Farahmand, F. (2016). Fundamentals of microprocessor and microcontroller [Lecture notes]. Retrieved from Sonoma State University. John, L. (n.d.). Bus Architecture [PDF File]. Retrieved on January 11, 2021, from http://www.eolss.net/sample- chapters/c15/e6-45-02-07.pdf Roosta. R. (n.d.). Computer bus structures [PDF File]. Retrieved on January 11, 2021, from http://www.csun.edu/~edaasic/roosta/BUS_Structures.pdf Toomsalu, A. (n.d.). Microprocessor Systems I – Microprocessor systems architecture [Lecture notes]. Retrieved from Tallin University of Technology – Department of Computer Engineering. Tristate Logic. (n.d.). In Reviseomatic.org. Retrieved on December 14, 2020, from https://reviseomatic.org/help/2- assembler/Assembler%20Tristate%20Logic.php What is bus arbitration in computer organization? (n.d.). In Tutorialspoint.com. Retrieved on January 11, 2021 from https://www.tutorialspoint.com/what-is-bus-arbitration-in-computer-organization 01 Handout 1 *Property of STI  [email protected] Page 4 of 4