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Questions and Answers
What is the primary function of the ES register in some string operations?
To handle memory addressing
What registers were introduced in the 80386 processor to handle storage requirements?
FS and GS registers
What is the content of the IP register, and how is it used?
The offset address of the next instruction to be fetched and executed by the CPU, and it's added to the CS register to obtain the real address of an instruction.
What is the main difference between the SP and BP registers?
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What is the primary function of the SI register?
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What is the purpose of the Flags register?
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What do the Status Flags reflect?
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What is the purpose of the Control Flags?
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What is the main difference between 3-address, 2-address, and 1-address instructions?
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What is the purpose of the MOVE instruction in the 2-address instruction example?
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What is the benefit of having fewer addresses per instruction?
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What is the trade-off for having fewer addresses per instruction?
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What type of memory organization is applicable to zero-address instructions?
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What is the name of the instruction that loads a value into the accumulator (AC) in the 1-address instruction example?
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What is the purpose of the STOR instruction in the 1-address instruction example?
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What is a fundamental design decision in computer architecture?
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What is the feature size of the processor that has 167 million transistors?
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What is the purpose of the Segment Register in the CPU?
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What is the function of the Bus Interface Unit (BIU) in the Intel 8086?
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What is the maximum addressable memory for all the processors listed in Table 6.4?
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What is the purpose of the Code Segment in a program?
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What is the name of the register that stores the address of the Stack Segment?
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What are the three main segments for the programming process?
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What is the purpose of the Flag Register in the Intel 8086?
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What is the primary function of the Program Counter (PC) in addressing modes?
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In Base-Register Addressing, what does R hold?
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What is the formula for Effective Address (EA) in Indexed Addressing?
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What is the primary application of Indexed Addressing?
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What is the key characteristic of Displacement Addressing?
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What happens to keyboard inputs when the IF (interrupt flag) is cleared?
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What determines the operation of the CPU?
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How does Relative Addressing differ from other addressing modes?
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What are the three areas where operands can be located?
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What is the primary feature of Stack Addressing Mode?
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What is the purpose of the Top of Stack register in Stack Addressing Mode?
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Why is it not efficient to put all the information required by the CPU in a machine instruction?
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What are the advantages of having all the information required by the CPU within one instruction or format?
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What are the three types of instruction formats to address the problem of long instructions?
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What are opcodes or operation codes represented by?
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What is the purpose of dividing an instruction into opcode and address fields?
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Study Notes
Recent Processors
- Transistors:
- 9.5 million (feature size: 250 nm)
- 42 million (feature size: 180 nm)
- 167 million (feature size: 65 nm)
- 820 million (feature size: 45 nm)
- Addressable memory: 64 GB
- Virtual memory: 64 TB
- Cache sizes: 512 kB L2, 256 kB L2, 2 MB L2, 6 MB L2
Organization of Intel Microprocessors
- Registers are divided into three categories:
- General Purpose Registers
- Address Registers (Segment, Pointer, Index)
- Status or Flag register
- Figure 6.1: Block Diagram of Intel 8086
- EU: Execution Unit
- BIU: Bus Interface Unit
- ALU: Arithmetic Logic Unit
- CU: Control Unit
- Flag register
- Instruction Pointer (Program Counter)
- Segment registers (CS, DS, ES, SS)
Segment and Addressing
- A segment is a special area in memory defined by a program
- Segment position in memory is not fixed and can be determined by the programmer
- 3 main segments:
- Code Segment (CS)
- Data Segment (DS)
- Stack Segment (SS)
- Segment registers:
- CS Register (Code Segment)
- DS Register (Data Segment)
- SS Register (Stack Segment)
- ES Register (Extra Segment)
- FS and GS Registers (Additional Extra Segment)
Pointer Registers
- Instruction Pointer (IP) register:
- Contains the offset address of the next instruction
- Content added to CS register to obtain real address
- Stack Pointer (SP) register:
- Used with SS register to access stack segment
- Base Pointer (BP) register:
- Used primarily to access data on the stack
- Can also be used to access data in other segments
- Index Register:
- Source Index (SI) register:
- Points to memory locations in data segment addressed by DS
- Incrementing SI accesses consecutive memory locations
- Destination Index (DI) register:
- Used in string operations to access memory locations addressed by ES
- Source Index (SI) register:
Status Flags Register
- Two kinds of flags:
- Status flags (reflect result of an instruction)
- Control flags (enable or disable certain operations)
- Examples:
- ZF (Zero Flag): set to 1 if result of subtraction is 0
- IF (Interrupt Flag): cleared to 0, inputs from keyboard are ignored
Instruction Format
- CPU's instruction set: collection of different instructions that CPU can execute
- Each instruction must contain:
- Operation code (opcode)
- Source operand reference
- Result operand reference
- Next instruction reference
- Instruction format:
- Opcode and address
- Operands can be in:
- Main or virtual memory
- CPU register
- I/O device
- Addressing modes:
- 1-address instruction
- 2-address instruction
- 3-address instruction
Instruction Addressing Modes
- Base-Register Addressing:
- A holds displacement
- R holds pointer to base address
- R may be explicit or implicit
- Indexed Addressing:
- A = base
- R = displacement
- EA = A + R
- Good for accessing arrays
- Displacement Addressing:
- Instruction specifies displacement
- Relative Addressing:
- Instruction specifies displacement relative to program counter
- Stack Addressing Mode:
- Operand is implicitly on top of stack
- Example: ADD pops top two items from stack and adds
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Description
This quiz covers the features and specifications of various recent processors, including the number of transistors, feature size, addressable memory, virtual memory, and cache size.
