Chapter 6 Part 1_Instruction Set.ppt

CHAPTER 6 PART 1 INSTRUCTION SET : Organization of Intel PC and the Instruction Format 1  Topics 6.1 Introduction 6.2 Organization of Intel Microprocessor 6.3 Instruction Format 6.4 Addressing Mode 2 6.1) Introduction...

CHAPTER 6 PART 1 INSTRUCTION SET : Organization of Intel PC and the Instruction Format 1  Topics 6.1 Introduction 6.2 Organization of Intel Microprocessor 6.3 Instruction Format 6.4 Addressing Mode 2 6.1) Introduction Intel 4004 was the first chip to contain all of the components of a CPU on a single chip (1971 : the first microprocessor )  In 1972, Intel 8008 was introduced and it was the first 8-bit microprocessor.  Both 4004 and 8008 had been designed for specific applications.  In 1974, Intel 8080 was designed to be the CPU of a general-purpose microcomputer. 3 Table 6.1, Table 6.2, Table 6.3 and Table 6.4 are the evolution of Intel Microprocessors: 4004 8008 8080 8086 8088 Introduced 1971 1972 1974 1978 1979 Clock speeds 108 kHz 108 kHz 2 MHz 5 MHz 5 MHz 8 MHz 8 MHz 10 MHz Bus width 4 bits 8 bits 8 bits 16 bits 8 bits Num. of transistors 2300 3500 6000 29000 29000 Feature size (m) 10 6 3 6 Addressable 640 Bytes 16 KB 64 KB 1 MB 1 MB memory Table 6.1 : 1970s Processors 4  80286 386TM DX 386TM SX 486TM DX CPU Introduced 1982 1985 1988 1989 Clock speeds 6 – 12.5 16 – 33 16 – 33 25 - 50 MHz MHz MHz MHz Bus width 16 bits 32 bits 16 bits 32 bits Num. of 134000 275000 275000 1.2 million transistors Feature size (m) 1.5 1 1 0.8 - 1 Addressable 16 MB 4 GB 16 MB 4 GB memory Virtual memory 1 GB 64 TB 64 TB 64 TB Cache - - - 8 kB Table 6.2 : 1980s Processors 5  486TM SX Pentium Pentium Pro Pentium II Introduced 1991 1993 1995 1997 Clock speeds 16 – 33 60 – 166 150 – 200 200 - 300 MHz MHz MHz MHz Bus width 32 bits 32 bits 64 bits 64 bits Num. of 1.185 3.1 million 5.5 million 7.5 million transistors million Feature size (m) 1 0.8 0.6 0.35 Addressable 4 GB 4 GB 64 GB 64 GB memory Virtual memory 64 TB 64 TB 64 TB 64 TB Cache 8 kB 8 kB 512 kB L1 512 kB L2 and 1 MB L2 Table 6.3 : 1990s Processors 6  Pentium III Pentium 4 Core 2 Duo Core 2 Quad Introduced 1999 2000 2006 2008 Clock speeds 450 – 660 1.3 – 1.8 1.06 – 1.2 3 GHz MHz GHz GHz Bus width 64 bits 64 bits 64 bits 64 bits Num. of 9.5 million 42 million 167 million 820 million transistors Feature size (nm) 250 180 65 45 Addressable 64 GB 64 GB 64 GB 64 GB memory Virtual memory 64 TB 64 TB 64 TB 64 TB Cache 512 kB L2 256 kB L2 2 MB L2 6 MB L2 Table 6.4 : Recent Processors 7 6.2) The Organization of Intel Microprocessors  Figure 9.1 below is a block diagram of Intel 8086. The registers are divided into three categories:  General Purpose Registers  Address Registers  Segment register  Pointer Register  Index Register  Status or Flag register 8  EU : Execution Unit BIU : Bus Interface Unit AX AH AL BX BH BL CX CH CL Program Control DX DH DL CS SP BP DS SI SS DI ES Bus Bus Control Unit ALU 1 CU 2 Flag register 3 Instruction 4 Queue Instruction Pointer n (Program Counter) Figure 6.1: Block Diagram of Intel 8086 9 Segment And Addressing  Segment is a special area in a memory that is defined in a program  The segment position in a memory is not fixed and can be determined by the programmer  3 main segments for the programming process are:  Code Segment  Data Segment  Stack Segment 10  Contains the starting address of each segment SS Register Address Stack segment DS Register Address Data segment CS Register Address Code segment Segment registers (in the CPU) memory (MM) 11  Code Segment (CS) Contains the machine instructions/codes that are going to be executed in a CPU. Typically, the first executable instruction is at the beginning of this segment, and the operating system links to that location to begin program execution. CS register (in a CPU) will hold the starting address of the Code Segment. Data Segment (DS) Contains a program’s defined data, constants and works areas. 12  DS register will hold the starting address of the Data Segment.  Stack Segmen (SS) Contains any data or address that the program needs to save temporarily. SS register will hold the starting address of the Stack Segment. 13 Segment Offsets  All memory locations within a segment are relative to the segment’s starting address.  The distance in bytes from the first location of the segment to another location within the segment is expressed as an offset.  Thus the first location of the code segment is at offset 00, the second location is at offset 01 and so forth.  In Intel series, the location is in term of byte. 14   To refer any memory location in a segment, the processor combines the value in a segment register with the offset value of that location. Eg: A starting address of data segment is 038E0H, so the value in DS register is 038E0H. An instruction refers a location with an offset of 0032H bytes from the start of the data segment. the actual address is: = [DS register] + offset = 38E0H + 0032H = 3912H 15  Intel CPU Registers General Purpose Registers There are four 16-bit general purpose registers that can be accessed separately the high and low bytes of the registers.  AX register (Accumulator register) is the preferred register to use in arithmetic, logic, and data transfer instruction because its generates the shortest machine code. in multiplication and division operations, one of the numbers involved must be in AX or AL. 16  I/O operations also require the use of AX and AL. AH AL AX EAX  BX register (Base register) beside used for computation, it also serves as an address register. An example is a table look- up instruction. BH BL AX EAX 17   CX register (Count register) serves as a loop counter (CX) and also as a count in instructions that shift and rotate bits. Also as a data register in arithmetic operations. CH CL CX ECX  DX register (Data register) uses in multiplication and division and also I/O operations. also as a data register in an arithmetic operations DH DL DX EDX 18 Address Registers  Segment Registers There are 6 segment registers: i) Code Segment (CS) register  Contains the starting address of a code segment.  The content of CS register will be added to the content in Instruction Pointer (IP) register to obtain the address of an instruction (in the MM) that are going to be fetched by the CPU. 19 ii) Data Segment (DS) register  Contains the starting address of a data segment.  The content of DS register will be added to the value in the address field of an instruction format to obtain the real address of the data in a data segment. iii) Stack Segment (SS) register  Contains the starting address of a stack segment. 20   The content of SS register will be added to the content in the Stack Pointer (SP) register to obtain the required word. iv) Extra Segment (ES) register  Used by some string (character data) operations to handle memory addressing  ES register is associated Data Index (DI) register. v) FS and GS Registers Additional extra segment registers introduced in 80386 to handling storage requirement. 21  Pointer Registers i) Instruction Pointer (IP) register  contains the offset address of the next instruction that will be fetched and executed by the CPU The content of the IP register will be added to the content of the CS register to obtain the real address of an instruction. ii) Stack Pointer (SP) register  is used in conjunction with SS register for accessing the stack segment. 22  iii) Base Pointer (BP) register  is used primarily to access data on the stack.  unlike SP, BP can also be used to access data in the other segments. Index Register i) Source Index (SI) register  is used to point the memory locations in the data segment addressed by DS.  by incrementing the content of SI, consecutive memory location can easily be accessed 23  ii) Destination Index (DI) register  perform the same function as SI register.  used in string operations to access memory locations addressed by ES.  Status of Flags register  the purpose is to indicate the status of the microprocessor by setting the individual bits of the register.  two kinds of flags: status flags and control flags 24 i) The Status Flags reflect the result of an instruction executed by the processor. example when a subtraction operation result is a 0, the ZF (zero flag) is set to 1 (true). ii) The Control Flags enable or disable certain operations of the processor. example if the IF (interrupt flag) is cleared (set to 0), inputs from the keyboard are ignored by the processor. 25 6.3) Instruction Format  The operation of the CPU is determined by the instructions it executes (machine or computer instructions).  CPU’s instruction set – the collection of different instructions that CPU can execute. 26  Each instruction must contain the information required by the CPU for the execution as listed below:  Operation code – opcode  Source operand reference  Result operand reference  Next instruction reference      Instruction Format 27  Operands (source & result) can be in one of the 3 areas:-  Main or Virtual Memory  CPU register  I/O device  It is not efficient to put all the information required by CPU in a machine instruction  Each instruction is represented by sequence of bits and is divided into 2 fields; opcode & address opcode address 28  Processing become faster if all information required by the CPU are within one instruction or one instruction format  Problems  instruction become long (takes a few words in a main memory to store one single instruction)  Solution  provide a few instruction formats;  1-address instruction  2-address instruction  3-address instruction 29  Opcodes or operation codes are represented by abbreviations, called mnemonics, that indicate the operation. Common examples: ADD Add SUB Subtract DIV Divide MUL Multiply LOAD Load data from memory STOR Store data to memory 30 3-address Instruction Opcode address for Result address for Operand 1 address for Operand 2 Example : SUB Y A B Y=A-B Opcode: SUB Result: Y Operand 1: A Operand 2: B Address for Next instruction: in a special register that called program counter (PC) 31 2-address Instruction opcode address for Operand 1 & Result address for Operand 2  Example : SUB Y B Y=Y–B Opcode: SUB Operand 1: Y Operand 2: B Result: replace operand 1, Y Next instruction: in a special register that called program counter (PC) 32 1-address Instruction opcode address for Operand 2  Example : LOAD A SUB B AC = AC - B Opcode: SUB Operand 1: in a special register called accumulator (AC) Operand 2: B Result: replace operand 1, AC Next instruction: in a special register called program 33 counter (PC) What is the maximum number of addresses one might need in an instruction? Example: Write a program using 1, 2 and 3-address instruction to compute: Y = (A-B) / (C+D x E) Note: Do not alter the value of any of the operand locations. 34 3-address Instruction Y = (A-B) / (C+D x E) Instruction Comment SUB Y, A, B Y A-B MPY T, D, E T DxE ADD T, T, C T T+C DIV Y, Y, T Y Y/ T 35 2-address Instruction Y = (A-B) / (C+D x E) Instructions Comment: MOVE Y, A Y A SUB Y, B Y Y–B MOVE T, D T D MPY T, E T T*E ADD T, C T T+C DIV Y, T Y Y/T 36 1-address Instruction Y = (A-B) / (C+D x E) Instructions Comment LOAD D AC D MPY E AC AC x E ADD C AC AC + C STOR Y Y AC LOAD A AC A SUB B AC AC – B DIV Y AC AC / Y STOR Y Y AC 37  Utilization of Instruction Addresses (Nonbranching Instructions) ** Zero-address instructions are applicable to a special memory organisation, called a stack. 38 The number of addresses per instruction is a basic design decisions Fewer addresses per instruction result in more primitive instructions, require less complex CPU, also shorter length of instructions. On the other hand, programs contain more total instructions, which in general results in longer execution times and longer, more complex programs. 39  An important threshold between one address and multiple address instructions is for one address instructions: the programmer generally has available only one general purpose register, the accumulator but for multiple address instructions, it is common to have multiple general purpose registers 40 Design trade offs involved in choosing the number of addresses per instruction are complicated by other factors Issue of whether an address references a memory location or a register A machine may offer a variety of addressing modes and the specification of mode takes one or more bits The result is that most CPU designs involve a variety of instruction formats 41 6.4) Addressing Mode Address field  address for operand & result number of bit required to store data (operand & result) Eg: Field size = 4 bit  operand value = 4 bit value (00002 11112)  operand address = 24 =16 address space. How is the address of an operand specified? 42 Addressing Mode (Cont.) Addressing mode – refer to the mode of address field in an instruction format The most common addressing modes are: Immediate Direct Indirect Register Register Indirect Displacement Stack 43 Immediate Addressing Mode Address field  the data or operand value Instruction opcode address Address field contain the real data or operand value Eg: ADD 20  Operand value = 20  add 20 to contents of accumulator (AC) AC AC + 20 Assume that the initial value in AC = 10.  AC AC + 20  AC 10 + 20 = 30 44 Advantages:  No memory reference to fetch data  Fast Disadvantage:  Limited operand magnitude because the size of the number is restricted to the size of the address field (small compared with the word length.) 45 Direct Addressing Mode Address field  address of operand in memory Eg. ADD A Look in memory at location with an address A for operand value Add contents of word A to AC and store the result back to AC AC = AC + M(A) 46 Advantages: One memory reference to access data No additional calculations to work out to get an effective address Disadvantage: Limited address space (the length of address field is less than the word length) Instruction Opcode A Memory A Operand value 47  Indirect Addressing Mode Address field  address of a memory word that contain the actual address of an operand. Eg. ADD A Look in memory at location or word with address A. The actual address of an operand is in this word. (assume that the value in word A = B) Add contents of word B to AC and store the result back to AC AC = AC + M(M(A)) = AC + M(B) 48 Advantage:  Bigger address space (compare with direct addressing mode) Disadvantage: Multiple memory accesses to find operand (hence slower access time) Instruction Opcode A Memory A Point to operand (B) B Operand 49 Register Direct Addressing Mode the operand is held in a register named in address field opcode Register address Advantages:  Small address field is needed  No memory references are required  Fast execution Disadvantage:  Very limited address space 50 Eg.: ADD R The operand value is in a register Add contents of register R to AC and store the result back to AC AC = AC + (R) Instruction Opcode Register Address R Registers R Operand value 51 Register Indirect Addressing Mode Instruction Opcode Register Address R Memory Registers R Pointer to Operand (B) B Operand value 52  Is analogous to indirect addressing Address field refers to a register Operand value is in a memory word or location pointed by a content of a register Advantage:  Bigger address space (same as indirect addressing) Disadvantages:  Multiple memory accesses to find operand, hence slower access time (but faster than indirect addressing) 53 Displacement Addressing Mode____ Combines the capabilities of direct addressing & register indirect addressing Known by a variety of names depending on the context of its use Requires that the instruction has two address fields Address field hold two values – A = base value – R = register that holds displacement – or vice versa Effective address = A + (R) 54  Instruction Opcode Register R Address A Memory Registers Pointer to Operand + Operand 55  Displacement Addressing ( Continue) Common uses of displacement addressing: – Relative Addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC – Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86 – Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays – EA = A + R – R++ 56 Displacement Addressing Instruction Opcode Address A Memory Program Counter PC + Operand Instruction Opcode Address A Relative Addressing Memory Instruction Opcode Address A Memory Index Register + Operand Registers Base Register + Operand Indexed Addressing Base-Register Addressing 57  Stack Addressing Mode Operand is (implicitly) on top of stack e.g. – ADD Pop top two items from stack and add Instruction Opcode Operand Top of stack implicit Top of stack register 58 59