Computer Architecture and Organization Exam
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Questions and Answers

Which directive is used to define an 8-bit (1-byte) memory variable in assembly language?

  • dd
  • dq
  • Dw
  • db (correct)

In assembly language, which directive would you use to define a 16-bit (2 bytes) memory variable?

  • dd
  • dq
  • Db
  • dw (correct)

What does the dd directive define in terms of memory size?

  • A 64-bit (8 bytes) memory variable
  • A 32-bit (4 bytes) memory variable (correct)
  • A 128-bit (16 bytes) memory variable
  • An 8-bit (1 byte) memory variable

Which directive is used in assembly language to define a 10-byte (80-bit) memory variable?

<p>dt (C)</p> Signup and view all the answers

Which directive would you use to define a 64-bit (8 bytes) memory variable in assembly language?

<p>dq (C)</p> Signup and view all the answers

Which term describes the underlying implementation of computer architecture that is transparent to the programmer?

<p>Computer Organization (A)</p> Signup and view all the answers

Which architecture is also known as Fetch-Decode-Execute Architecture?

<p>Von Neumann Architecture (A)</p> Signup and view all the answers

What is the term that represents the signal in cycles per second?

<p>Frequency (C)</p> Signup and view all the answers

According to Flynn’s Classification, Von Neumann Machines are classified as which type?

<p>SISD (D)</p> Signup and view all the answers

What is the processing style also known as SIMD?

<p>All of the above (D)</p> Signup and view all the answers

In a Microprogrammed Control Unit, what is the sequence of control words referred to as?

<p>Microroutine (A)</p> Signup and view all the answers

What is the time required to perform a single memory reference (read or write) called?

<p>Memory Cycle (A)</p> Signup and view all the answers

What is the term that describes the product of instruction count, cycle per instruction, and the period?

<p>CPU Time (C)</p> Signup and view all the answers

What is the addressing mode in which the effective memory address is held following the instruction opcode?

<p>Register Indirect (D)</p> Signup and view all the answers

Which classification method is most widely used for classifying computers?

<p>Flynn’s Classification of Computers (C)</p> Signup and view all the answers

Which of the following describes an operand in assembly language?

<p>Operand (B)</p> Signup and view all the answers

In which part of a computer are data fetched from memory?

<p>Memory Unit (C)</p> Signup and view all the answers

What type of memory is internal to the CPU and operates at high speeds?

<p>Register (A)</p> Signup and view all the answers

Which unit is responsible for executing instructions in a computer?

<p>Instruction Unit (A)</p> Signup and view all the answers

Which language corresponds directly with computer instructions and supports microinstructions?

<p>Assembly language (B)</p> Signup and view all the answers

What does the Memory Data Register (MDR) store?

<p>Data to be written or read (B)</p> Signup and view all the answers

What is the numeric value utilized as a reference in calculating addresses during program execution?

<p>Offset address (B)</p> Signup and view all the answers

What is the first action the processor takes to fetch data from memory?

<p>Send the memory address (B)</p> Signup and view all the answers

What is the name of the special-purpose register that holds the address of the next instruction to be executed?

<p>Instruction address register (A)</p> Signup and view all the answers

What happens second when a processor fetches data from memory?

<p>Send the memory read signal (A)</p> Signup and view all the answers

Which port is considered the primary port on all computer systems?

<p>Keyboard port (C)</p> Signup and view all the answers

Which statement accurately describes the relationship between the number of bits in the MDR and the word size of a computer?

<p>Varies based on memory organization (C)</p> Signup and view all the answers

Which segment register contains the program or code for the next instruction in the 8086/8088 architecture?

<p>Code segment (B)</p> Signup and view all the answers

In the given instruction R1  [R1] + [LOC], what is the fourth step in its execution?

<p>Offset-field-of-IRout, MARin, Read (D)</p> Signup and view all the answers

The number of bits in the Memory Address Register (MAR) primarily depends on which of the following?

<p>How memory is organized. (C)</p> Signup and view all the answers

How can Step I of the instruction execution process be symbolically represented?

<p>[IR]  [PC] (B)</p> Signup and view all the answers

Which statement best describes the process that occurs after fetching the contents into the Instruction Register (IR)?

<p>The contents of the MAR are transferred to the IR. (B)</p> Signup and view all the answers

What control signals are relevant during Step I of instruction execution?

<p>MDRout, IRin (C)</p> Signup and view all the answers

Why are the actions of Step II needed when executing instructions?

<p>They are unneeded when an absolute jump instruction follows. (D)</p> Signup and view all the answers

During the process of Step II, what must occur regarding the Program Counter (PC)?

<p>The data lines must clear before any operations. (B)</p> Signup and view all the answers

Which additional control signal is required to execute Step II, along with PCout, Select1, and Add?

<p>MARin (A)</p> Signup and view all the answers

When an instruction requires data to be fetched from memory, which register commonly stores the address to be accessed?

<p>R1 (C)</p> Signup and view all the answers

Based on the logic equation for MDRout, which instructions utilize the Memory Data Register (MDR) during the fetch cycle?

<p>Only INS2 and INS3 (D)</p> Signup and view all the answers

What does the logic equation WMFC = T2 + T5 + T6·INS2 + T6·INS3 + T7·INS3 tell us about the Write Memory Function Control (WMFC) signal?

<p>The WMFC signal is asserted when the CPU is writing data to memory. (B)</p> Signup and view all the answers

What is the purpose of the MARin = T1 + T4 + T6·INS2 + T6·INS3 + T7·INS3 logic equation?

<p>To control the writing of data into the MAR. (C)</p> Signup and view all the answers

During time slot T3, which of the following actions is occurring in the simplified computer?

<p>The CPU is fetching the next instruction from memory. (B)</p> Signup and view all the answers

What happens during time slot T2?

<p>The PC is loaded with the next instruction address. (B)</p> Signup and view all the answers

The logic equation for Zout indicates that the ALU is used for instructions:

<p>All three instructions: INS1, INS2, and INS3 (D)</p> Signup and view all the answers

What is the correct interpretation of the PCout = T1 logic equation?

<p>The contents of the PC are transferred to the internal bus at time T1. (D)</p> Signup and view all the answers

What can we conclude about instruction INS2 from the logic equations provided?

<p>INS2 reads data from memory at times T6 and T7 and also performs an Arithmetic Logic Unit (ALU) operation. (C)</p> Signup and view all the answers

Flashcards

Flynn's Classification of Computers

A classification method based on the way instructions are processed and data is accessed by the processor.

Memory Unit

The component responsible for storing data and instructions.

Processor Unit

The component responsible for executing instructions fetched from memory.

Memory Address Register (MAR)

A register that holds the memory address for the data to be read or written.

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Fetching Data from Memory: Step 1

The first action the processor takes to retrieve data from memory is sending the memory address to the MAR.

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Fetching Data from Memory: Step 2

The second action the processor takes to retrieve data from memory is sending a read signal to the memory unit.

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MDR and Word Size

The number of bits in the MDR is equal to the word size of a computer.

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MDRout, IRin

It involves loading data from memory into a register, typically the MDR.

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Computer Organization

The underlying implementation of the computer architecture hidden from the programmer. It focuses on the hardware aspects, like how data is moved and processed.

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Computer Architecture

Defines the instruction set, addressing modes, data types, and other aspects visible to the programmer. It's like the 'blueprint' of the computer.

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Von Neumann Architecture

A computer architecture where instructions and data are stored in a single address space, fetched and executed sequentially. Also known as 'Fetch-Decode-Execute' architecture.

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Flynn's Classification

A classification of computer architectures based on the number of instruction streams and data streams processed simultaneously.

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SIMD (Single Instruction, Multiple Data)

A type of computer architecture where a single instruction stream operates on multiple data streams simultaneously. It's like performing the same operation on many values at once.

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MIMD (Multiple Instruction, Multiple Data)

A type of computer architecture where multiple instruction streams, each operating on a different data stream, are executed simultaneously. It's like having multiple teams working on different tasks.

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Period

The inverse of the clock rate, representing the time taken for one cycle of the clock.

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Microprogram

The sequence of control words used by a Microprogrammed Control Unit to execute instructions. Each word defines the control signals needed for a specific operation.

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What does the MAR store?

The Memory Address Register (MAR) stores the address of the memory location to be accessed by the processor.

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How does the MAR size affect memory?

The size of the Memory Address Register (MAR) determines the maximum amount of memory that can be addressed by the processor.

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What is the role of the Program Counter (PC)?

The PC (Program Counter) holds the address of the next instruction to be fetched and executed. It is incremented after each instruction fetch.

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What happens during the instruction fetch step?

The fetch operation involves copying the instruction from the memory location pointed to by the PC into the Instruction Register (IR).

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What happens during the decode step?

The decode operation involves analyzing the instruction in the IR to determine the operation to be performed and the operands involved.

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What happens during the execute step?

The execute operation involves carrying out the actions specified by the instruction in the IR. This might involve performing an arithmetic operation, moving data, or making a decision.

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What is an absolute jump instruction?

An absolute jump instruction alters the flow of control and directly changes the program counter (PC) to a specific memory location.

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What are control signals?

Control signals govern the flow of data within the processor and between the processor and memory. They control the operation of various components, such as registers, memory, and buses.

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What does the db directive do?

Directives are used to define data variables in assembly language. The db directive declares an 8-bit variable that will store a single byte of data.

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What is the dw directive for?

The dw directive is used to define 16-bit (2 bytes) memory variables. Think of it as defining a 'word' of data.

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What does the dd directive define?

The dd directive stands for 'define double word' and is used to define 32-bit (4 bytes) memory variables. This allows you to store larger values.

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What is the dq directive used for?

The dq directive stands for 'define quad word' and is used to define 64-bit (8 bytes) memory variables. This is used to store even larger values.

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How do you define a 10-byte variable?

To define a 10-byte (80-bit) memory variable, you would use the directive dt, which stands for 'define ten bytes'.

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What is the MAR?

The Memory Address Register (MAR) holds the address of the memory location to be accessed.

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What is the MDR?

The Memory Data Register (MDR) holds the data that is being read from or written to memory.

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Explain the instruction fetching process.

The process of fetching an instruction from memory involves the following steps:

  1. MAR  [PC] (Load the Program Counter value into the MAR)
  2. Read (Read the instruction from memory using the address in the MAR)
  3. Wait for MFC signal (Wait for the Memory-to-CPU (MFC) signal indicating data is ready in MDR)
  4. R1  [MDR] (Transfer the instruction from the MDR to a register (R1)).
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What does T1 represent in the logic equations?

T1 in the logic equation represents the time slot when the program counter (PC) value is loaded into the MAR.

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Explain WMFC in the context of the logic equations.

The WMFC signal indicates when the CPU can write data to memory. In the logic equations, it shows which instructions access memory locations at specific time slots.

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What operations does INS3 perform based on the logic equations?

INS3 performed a read or write operation at either time T5 or T6, as indicated by the logic equations. It also accessed a memory location at T10.

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What can the CPU do during the fetching process (steps 2 & 3)?

The CPU can execute instructions that don't directly involve memory access during steps 2 and 3. The CPU may perform these tasks concurrently with the memory operations.

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What was the first microprocessor made by Intel?

The Intel 4004 was the first microprocessor released in 1971.

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Direct Addressing

An addressing mode where the memory location directly following the instruction opcode specifies the effective memory address (EA). This means the instruction directly points to the data's location.

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Operand

In a computer, the operand is the data value that an instruction operates on.

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Register

The register is a high-speed memory location within the CPU, holding data values used frequently by the processor.

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CPU Register

The CPU registers are small, very fast storage areas located within the CPU. They hold temporary data values for fast processing.

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Accumulator

The Accmulator is a specialized register in a single-address instruction format. It holds the result of an arithmetic or logical operation.

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Base Address

The base address is a numeric value used as a reference point for calculating the addresses of memory locations accessed in a computer program.

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Instruction Address Register (IAR)

The Instruction Address Register (IAR) is a special-purpose register in the control unit of a CPU. It stores the address of the next instruction to be fetched and executed from memory.

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Code Segment Register

The Code Segment register is a special register in the 8086/8088 processors. It's used to store the memory segment containing the program instructions.

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Study Notes

Computer Architecture and Organization Exam

  • Pledge of Honor: Students pledge to uphold academic honesty during the exam. Dishonesty will result in serious sanctions.
  • General Instructions: Follow all instructions carefully. Use only non-red ink and do not leave your seat without permission. Talking to or looking at seatmates is considered cheating.
  • Multiple Choice: Select the best answer from the options provided on the answer sheet. Mark incorrect answers with a cross (X) and write the correct answer in the space corresponding to the best choice.

Computer Organization and Architecture

  • Computer Organization: The implementation design of the computer, hidden from the programmer, but underlying the architecture.
  • Computer Architecture: The design of a computer's components and their communication, visible to the programmer, encompassing the components.
  • Fetch-Decode-Execute Architecture: The fundamental cycle of a computer, where instructions are fetched, decoded, and executed.
  • Von Neumann Architecture: A computer architecture where data and instructions are stored in the same memory space.
  • Flynn's Classification: A method of classifying computer architectures based on the number of instruction streams and data streams. Von Neumann machines are SISD.
  • MIMD (Multiple Instruction, Multiple Data): Parallel processing with multiple independent processors, each executing a separate program and accessing separate data streams.
  • MISD (Multiple Instruction, Single Data): Not commonly used. Multiple instructions work on a single data stream.
  • Clock Rate and Period: The speed of a computer, measured in Hertz. Period is the inverse of the clock rate.
  • Memory Cycle: Time needed to perform a read or write to memory.
  • Instruction Register (IR): Holds the current instruction being executed.
  • Program Counter (PC): Holds the address of the next instruction to be fetched.
  • Memory Data Register (MDR): Temporarily stores data read from or written to memory.
  • Memory Address Register (MAR): Holds the address of the memory location to be accessed.

Instruction Execution

  • Instruction Fetch (Step 1): The PC contains the address of the next instruction. Contents of the memory location specified by the PC are fetched (loaded) into the instruction register (IR).
  • Instruction Decode (Step 2): The instruction in the IR is decoded to determine the operation that needs to be performed.
  • Execution (Step 3): The CPU performs the operation specified by the fetched instruction.

Memory Access

  • Memory Address and Data Transfer: Address is loaded into the memory address register and the data is transferred to the memory data register.

Additional Topics

  • Registers: Used to store intermediate values during instruction processing.
  • Arithmetic Logic Unit (ALU): Performs arithmetic and logic operations as specified by the instruction.
  • Control Unit: Manages the execution of instructions.
  • Data Path: The interconnections and components within a computer for transferring data.
  • Program Execution: Fetches, decodes, and executes a sequence of instructions.

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CMPE 30224 Computer Architecture and Organization Midterm Exam PUP PDF

Description

Test your knowledge of computer organization and architecture concepts, including the fundamental fetch-decode-execute cycle. This exam will evaluate your understanding of how hardware and software interact in computer systems. Be prepared to select the best answers and demonstrate your academic integrity.

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