CMPE 30224 Computer Architecture and Organization Midterm Exam PUP PDF

POLYTECHNIC UNIVERSITY OF THE PHILIPPINES COLLEGE OF ENGINEERING COMPUTER ENGINEERING DEPARTMENT MIDTERM DEPARTMENTAL EXAMINATION...

POLYTECHNIC UNIVERSITY OF THE PHILIPPINES COLLEGE OF ENGINEERING COMPUTER ENGINEERING DEPARTMENT MIDTERM DEPARTMENTAL EXAMINATION SCORE CMPE 30224 COMPUTER ARCHITECTURE AND ORGANIZATION Name: Student No.: Faculty Name: Date of Examination: Section: Schedule (Time/Day) : Pledge of Honor I, , a student of the Polytechnic University of the Philippines, pledge to exercise integrity and honesty as I take this examination. I consider it dishonest to ask for, give, or receive help in this examination. I pledge to do all that is in my power to live a life of dignity and credibility and to create that spirit in my environment. Student’s Signature Date GENERAL INSTRUCTIONS: 1. Follow all instructions carefully. Failure to do so will warrant a substantial deduction from your final score. 2. Write everything in non-red ink. No borrowing of pens, etc. 3. You cannot leave your seat unless you are through with the exam. If you have any questions, just raise your hand and the instructor or proctor will attend to you. 4. Talking to or looking at your seatmate (and his/her paper) is automatically considered cheating, which is subject to very serious sanctions as stipulated in the student handbook. GOOD LUCK!!! I. MULTIPLE CHOICE [100 points]. Choose the letter corresponding to the best choice. Use the Answer Sheet that has been attached to this examination questionnaire. Should you make a mistake (or decide to change your answer), put a distinctive cross mark (X) over your previous answer and write your answer in the space corresponding to the best choice. 1. It refers to the design of computers and understanding the components that make up the computer and the way they are interconnected. A. Computer Organization B. Computer Architecture C. Computer Methods D. None of the above 2. It is the underlying implementation of the architecture which is transparent to the programmer. A. Computer Organization B. Computer architecture C. Computer method D. None of the above 3. It is also known as Fetch-Decode-Execute Architecture. A. Von Neumann Architecture B. Flynn’s Architecture C. Computer Architecture D. None of the above 4. It is the signal in cycles per second. A. Period B. Frequency C. Duty Cycle D. Amplitude 5. According to Flynn’s Classification of Computers, Von Neumann Machines can be classified as: A. MIMD B. MISD C. SIMD D. SISD 6. The SIMD computer processing is also known as: A. Array processing B. Systolic arrays C. All of the above D. None of the above 7. They are parallel computers that involve several independent processors, each executing a different program and accessing its sequence of data items. A. SIMD B. MIMD C. MISD D. SISD 8. Multiple Instruction Stream over a Single Data Stream (MISD) is also known as: A. Array processing B. Systolic arrays C. All of the above D. None of the above 9. It is the inverse of the clock rate. A. Period or cycle time B. Frequency C. All of the above D. None of the above 10. In a Microprogrammed Control Unit, the sequence of control words is usually referred to as a: A. Microprogram counters B. Microinstruction C. Microroutine D. Microprogram memory 11. It is equal to the product of instruction count, cycle per instruction, and the period. A. Memory time B. CPU time C. Cache time D. MIPS 12. It is the time needed to complete one memory reference (read or write). A. Memory cycle B. CPU cycle C. Register cycle D. Data cycle 13. It is often called the Instruction Set Processor or simply processor. A. Memory Unit B. Processing Unit C. MAR D. Program Counter 14. It contains the memory address of the instruction to be executed. A. Memory Unit B. Processing Unit C. MAR D. Program Counter 15. It holds the address of the location to or from which data are to be transferred. A. Memory Unit B. Processing Unit C. MAR D. Program Counter 16. It contains the instruction that is being executed. A. Instruction Register B. Processing Unit C. MAR D. Program Counter 17. It contains the data to be written or read out of the addressed location. A. Memory Unit B. Processing Unit C. MDR D. Program Counter 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 1 of 6  18. To execute a program, the processor fetches how many at a time and performs the functions specified. A. One B. Two C. Three D. Four 19. The registers, the ALU, and the interconnecting bus are collectively referred to as: A. Data B. Data path C. MAR D. Bus 20. It is a combinational circuit that functions as a data selector. A. Decoder B. MUX C. ALU D. Encoder 21. It can be enhanced with better hardware technology, innovative architectural features, and efficient resource management. A. Program behavior B. Machine capability C. All of the above D. None of the above 22. It is affected by algorithm design, data structures, language efficiency, programmers' skills, and compiler technology. A. Program behavior B. Machine capability C. All of the above D. None of the above 23. It is a combinational circuit that performs arithmetic and logical operations. A. Decoder B. MUX C. ALU D. Encoder 24. It is a sequence of data including input, partial, or temporary results, called for by the instruction stream. A. Data Stream B. Instruction Stream C. Register Stream D. Step decoder 25. It is a sequence of instructions executed by a machine. A. Data Stream B. Instruction Stream C. Register Stream D. Step decoder 26. It is the most universally accepted method of classifying computers. A. Flynn’s Classification of Computers C. Von Neumann Architecture B. Flynn’s Computer Architecture D. Von Neumann Classification of Computers 27. It is a part of a computer where data are fetched. A. Control Unit B. Instruction Unit C. Processor Unit D. Memory Unit 28. It is a part of a computer where instructions are being executed. A. Control Unit B. Instruction Unit C. Processor Unit D. Memory Unit 29. Which register contains the data to be written or read out of the address location? A. IR B. MAR C. MDR D. PC 30. To fetch data from memory, the first thing the processor does is: A. send the memory address. B. send the memory read signal. C. Both (A) and (B) D. Either (A) or (B) 31. To fetch data from memory, the second thing the processor does is: A. send the memory address. B. send the memory read signal. C. Both (A) and (B) D. Either (A) or (B) 32. The number of bits in the MDR is equal to the word size of a computer. This statement is: A. obviously true. B. false, it depends on how memory is organized. C. false, it depends on the maximum amount of memory that can be connected to the processor. D. false, it depends on whether the machine is a personal computer, workstation, mainframe, or supercomputer. FOR QUESTIONS 33 THROUGH 35: Assume an instruction/notation, R1  [R1] + [LOC], in the execution of the complete instruction. 33.The fourth step is: A. MDRout, IRin C. Zout, PCin, Yin, WMFC B. Offset-field-of-IRout, MARin, Read D. R1  [MDR] 34.The fifth step is: A. MDRout, IRin C. R1out, Yin, WMFC B. Offset-field-of-IRout, MARin, Read D. R1  [MDR] 35.The sixth step is: A. MDRout, IRin C. MDRout, SelectY, Add, Zin, MARin B. Offset-field-of-IRout, MARin, Read D. MDRout, SelectY, Add, Zin FOR PROBLEMS 36 THROUGH 40: Consider the execution of an object code with 200,000 instructions on an 800-MHz processor. The program consists of four major types of instructions. The instruction mixes and a number of cycles needed for each instruction type are given below based on the result of a program trace experiment: Instruction Type Cycles Instruction Mix Arithmetic and logic 1 60% Load/store with cache hit 2 18% Branch 4 12% Memory reference with a cache miss 8 10% 36. The cycle time of the system is A. 125 ns B. 12.5 ns C. 1.25 ns D. None of the Above 37. How long will it take to execute all arithmetic and logic instructions? A. 90 s B. 120 s C. 150 s D. None of the Above 38. The total number of cycles consumed by the program is: A. 448,000 B. 560,000 C. 780,000 D. None of the Above 39. The execution time of the program is: 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 2 of 6  A. 560 s B. 780 s C. 920 s D. None of the Above 40. The MIPS rate of the program is: A. 0.9 MIPS B. 1.1 MIPS C. 2.2 MIPS D. None of the Above 41. In order to fetch data from memory, the first thing the processor does is: A. send the memory address. B. send the memory read signal C. Both (A) and (B) D. Either (A) or (B) 42. In order to fetch data from memory, the second thing the processor does is: A. send the memory address. B. send the memory read signal. C. Both (A) and (B) D. Either (A) or (B) 43. The number of bits in the MDR is equal to the word size of a computer. This statement is: A. obviously true. B. false, it depends on how memory is organized. C. false, it depends on the maximum amount of memory that can be connected to the processor. D. false, it depends on whether the machine is a personal computer, workstation, mainframe, or supercomputer. 44. The number of bits in the MAR depends on: A. how memory is organized. B. the word size of the computer. C. the maximum amount of memory that can be connected to the processor. D. None of the Above FOR QUESTIONS 45 THROUGH 50: Consider the following actions performed by the processor in executing one instruction. I. Fetch the contents of the memory location pointed to by the PC and load these into the instruction register (IR) II. Increment the contents of the program counter (PC) by 1 III. Carry out the actions specified by the instruction in the IR 45. Step I can be symbolically written as: A. [IR]  [PC] B. [IR]  [[PC]] C. IR  [PC] D. IR  [[PC]] 46. Step I can be more completely expressed by the following statement: After the contents of the appropriate memory location have been fetched: A. the contents of the IR are transferred to the MDR. B. the contents of the IR are transferred to the MAR. C. the contents of the MDR are transferred to the IR. D. the contents of the MAR are transferred to the IR. 47. Which of the following control signals may be performed during Step I? A. MDRout, IRin B. MARout, IRin C. MDRin, IRout D. MARin, IRout 48. The actions of Step II: A. are needed even if the next instruction is an absolute jump instruction. B. are not needed especially if the next instruction is an absolute jump instruction. C. involve shifting the contents of the PC by one bit to the right. D. involve shifting the contents of the PC by one bit to the left. 49. In performing the actions of Step II: A. the arithmetic-logic unit must be involved. B. the contents of the PC must be saved in memory location. C. the contents of the PC must be saved in a general-purpose register. D. the data lines of the internal bus must be clear of any signals. 50. The control signals needed to execute Step II involve PCout, Select1, Add, and: A. MARin B. Read C. Zin D. Yin FOR QUESTIONS 51 THROUGH 53: Assume that the address of the memory location to be accessed is in register R1 and that the memory data is to be loaded into register R2. Part of the sequence of operations needed to achieve this is given below. Step 1. MAR  [R1] Step 2. Read Step 3. Wait for the MFC signal 51. The fourth step is: A. R2  [MAR] B. R1  [MAR] C. R2  [MDR] D. R1  [MDR] 52. The duration of step 3 depends on: A. the actual instruction to be executed. B. the distance between the memory and the CPU. C. the speed of the memory used. D. the size of the memory used. 53. During the execution of Steps 2 and 3: A. the CPU can execute instructions that do not require the use of the MAR and the MDR. B. the CPU should remain idle. C. the CPU should continuously poll the memory. D. the CPU can increment the contents of the MAR. 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 3 of 6  FOR PROBLEMS 54 THROUGH 57: A very simplified computer has only three instructions INS1, INS2, and INS3. The logic equations of a selected number of control signals are given below. PCout = T1 MDRout = T3 + T6 + T7·INS2 + T7·INS3 + T8·INS3 WMFC = T2 + T5 + T6·INS2 + T6·INS3 + T7·INS3 Zout = T2 + T5 + T8·INS1 + T9·INS2 + T10·INS3 MARin = T1 + T4 + T6·INS2 + T6·INS3 + T7·INS3 54. Which of the following statements is/are true at time slot T1? A. The internal bus holds the contents of the program counter. B. The MAR releases its contents onto the internal bus. C. Both (A) and (B) D. Neither (A) nor (B) 55. Which of the following statements can be gleaned from the logic equation of the WMFC? A. Instruction INS1 accessed a memory location at time T1. B. Instruction INS2 accessed a memory location at time T1. C. Instruction INS3 accessed a memory location at time T1. D. All three instructions accessed a memory location at T1. 56. Which of the following statements is/are true for INS3? A. INS3 performed an arithmetic statement either at time T9 or T10. B. NS3 issued a read/write operation at time T5 or T6. C. Both (A) and (B) D. Neither (A) nor (B) 57. At time T4: A. all three instructions made use of the ALU. B. all three instructions incremented the program counter. C. Both (A) and (B) D. Neither (A) nor (B) 58. It is the first microprocessor released by Intel in 1971. A. 4040 B. 4004 C. 4400 D. None of the above 59. It is the number of memory locations in 8088/8086. A. 1,048,574 bytes B. 524,255 16-bit C. 1,048,578 bytes D. None of the above 60. It is part of the 8088/8086 microprocessor that prefetches the succeeding instructions while executing the current operation. A. Instruction pointer B. Execution unit C. Prefetch Queue D. None of the above 61. The physical memory of the 8088 contains two banks of memory. This statement is: A. Always true. C. False, it contains one bank only. B. False, it contains three banks of memory. D. False, it doesn’t contain a bank of memory. 62. It is the total number of memory locations dedicated for functions, storage, or pointers to interrupt, and reserved for future use. A. 128 bytes B. 108 bytes C. 16 bytes D. None of the above 63. It is a general-purpose register used to hold temporary results of an arithmetic or logic operation. A. Base register B. Data register C. Count register D. None of the above 64. It is the total number of unused bits in the status register. A. 7 bits B. 16 bits C. 9 bits D. None of the above 65. It is the flag that tells if there is a carry-out but no carry-in or vice versa in the most significant bit of the result of an arithmetic or logic operation. A. Overflow Flag B. Carry Flag C. Auxiliary Carry Flag D. None of the above 66. It is the flag that is set to 1 if there is a carry-out of bit-3 and is set to zero if there is no carry out from bit-3. A. Overflow Flag B. Carry Flag C. Auxiliary Carry Flag D. None of the above For #’s 67-70. Perform: 0110 1100 0011 1001 + 1110 0101 1101 0111 67. It is the value of the Parity Flag after performing the ADD operation. A. Zero (0) B. One (1) C. Cannot be determined D. None of the above 68. It is the value of the Sign Flag after performing the ADD operation. A. Zero (0) B. One (1) C. Cannot be determined D. None of the above 69. It is the value of the Carry Flag after performing the ADD operation. A. Zero (0) B. One (1) C. Cannot be determined D. None of the above 70. It is the value of the Overflow Flag after performing the ADD operation. A. Zero (0) B. One (1) C. Cannot be determined D. None of the above 71. It is the control flag that tells what type of interrupt is present in the operation. A. Direction Flag B. Interrupt Enable Flag C. Trap Flag D. None of the above 72. It is the term that refers to the division of the main memory. 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 4 of 6  A. Partition B. Byte C. Segment D. None of the above 73. What is the physical address of 5601H:5FFAH? A. B5FB0H B. 655A1H C. 5C00AH D. None of the above 74. Only four of the segments can be active at any one time. This statement is: A. Always true. B. False, it should be only one segment that can be active. C. False, it should be two segments that can be active. D. False, no segment can be active. 75. It is the segment used for string instructions. A. Code segment B. Extra segment C. Stack segment D. Data segment 76. It is the initial value of the stack pointer upon start-up of the microprocessor. A. 0000H B. FFFFH C. A000H D. None of the above 77. It is an addressing mode used when the source operand represents constant data. A. Register addressing B. Direct addressing C. Immediate addressing D. None of the above 78. It is an addressing mode in which the operand to be accessed is specified as residing in an internal register of the 8086/8088. A. Register addressing B. Direct addressing C. Immediate addressing D. Register Indirect 79. It is an addressing mode in which the location following the instruction opcode holds an effective memory address (EA) instead of data. A. Register addressing B. Direct addressing C. Immediate addressing D. Register Indirect 80. It is an entity in which an operand is performed. A. Opcode B. Operand C. Register D. None of the above 81. It is a high-speed memory internal to the CPU. A. Register B. Flip-flops C. System bus D. None of the above 82. It is a computer-oriented language whose instructions is usually in one-to-one correspondence with computer instructions and provides facilities such as the use of microinstructions. A. Machine language B. Assembly language C. Assembler D. None of the above 83. It is the name of the CPU register in a single-address instruction format. A. Accumulator B. Base register C. Count register D. Data Register 84. It is the numeric value that is used as a reference in the calculation of addresses in the execution of the computer program A. Base address B. Offset address C. Physical address D. None of the above 85. It is a Special-purpose register used to hold the address of the next instruction to be executed. A. Instruction address register B. General-purpose register C. Instruction register D. None of the above 86. It is considered the primary port on all computer systems. A. Mouse port B. Printer port C. Keyboard port D. None of the above 87. It is a segment register that contains the program or code in the next instruction executed by the 8086/8088 is generated by adding the contents of IP to the contents CS x 10H. A. Code segment B. Data segment C. Stack segment D. Extra Segment 88. Which of the following best describes assembly language programming? A. A high-level programming language that is portable across different hardware architectures B. A low-level programming language that is closely tied to a computer's hardware architecture C. A programming language used mainly for developing mobile applications D. A language that exclusively uses binary code for program instructions 89. In assembly language programming, what is primarily used instead of binary machine code (1s and 0s)? A. Source code in a high-level language B. Numeric operations and calculations C. Mnemonics and symbolic names D. Scripts and markup tags 90. Why is assembly language considered a low-level programming language? A. Because it operates independently of hardware architecture B. Because it allows direct interaction with the CPU, memory, and registers C. Because it is easier to write and understand than high-level languages D. Because it only uses graphical interfaces to control hardware 91. Which of the following is an advantage of using assembly language over high-level languages like C or Python? A. It provides a simpler way to write code that is easily readable by humans B. It allows precise control over hardware components C. It enables programs to run on any hardware architecture without modification D. It requires less memory than binary machine code 92. What is the purpose of using mnemonics in assembly language? A. To represent machine instructions in a human-readable form B. To execute code faster than binary machine code C. To create graphical user interfaces D. To store data in the memory 93. Which of the following mnemonics is used to move data in assembly language? A. ADD B. MOV C. SUB D. JMP 94. In TASM, what is the purpose of the “.MODEL” directive? A. To define the memory model of program B. To initialize the stack segment 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 5 of 6  C. To execute arithmetic operations D. To load external libraries 95. Which memory model in TASM is typically used for very small programs, such as COM files? A. SMALL B. TINY C. LARGE D. MEDIUM 96. In the SMALL memory model, how are code and data segments organized? A. Code and data fit within one segment each B. Code and data are combined into a single segment C. Code or data may exceed a single segment D. D. Code and data are loaded from external files 97. Which directive is used to define an 8-bit (1-byte) memory variable in assembly language? A. Dw B. dq C. db D. dd 98. In assembly language, which directive would you use to define a 16-bit (2 bytes) memory variable? A. Db B. dw C. dd D. dq 99. What does the dd directive define in terms of memory size? A. A 32-bit (4 bytes) memory variable B. An 8-bit (1 byte) memory variable C. A 64-bit (8 bytes) memory variable D. A 128-bit (16 bytes) memory variable 100. Which directive is used in assembly language to define a 10-byte (80-bit) memory variable? A. Db B. dw C. dq D. dt ****** END-OF-EXAM ****** "Strive not to be a success, but rather to be of value." --Albert Einstein-- 1SEM SY2024-2025 COMPUTER ARCHITECTURE AND ORGANIZATIONS Page 6 of 6