Computer Organization and Architecture Final Exam (Chapters 1-7)

The control unit (CU) manages the flow of data and instructions within the CPU. It acts as a conductor, orchestrating operations based on program instructions.

Register addressing mode utilizes a register to store the operand's address. The CPU directly fetches the data from the designated register.

The stack pointer (SP) acts as an index pointing to the topmost element in the stack, a memory area used for storing temporary data and function parameters.

Reduced Instruction Set Computer (RISC) architectures prioritize a smaller set of simple instructions, emphasizing speed and efficiency with a streamlined design.

The prefetch unit is responsible for retrieving instructions from memory proactively, anticipating the CPU's needs and reducing execution time.

False, the load/store architecture is used by RISC processors to access main memory directly, and it is more efficient using a smaller set of simple instructions. The register-memory architecture used by CISC processors offers a wider range of complex addressing modes.

False, a Harvard architecture distinguishes between instruction and data memory, allowing them to be accessed simultaneously for improved performance.

True, a microprogram is a sequence of micro-instructions, executed by the control unit. These instructions are stored in a special memory called the control store, which provides a flexible mechanism for implementing the CPU's functionality.

False, the fetch-decode-execute cycle involves fetching, interpreting (decoding), and executing an instruction one at a time. The process repeats for each subsequent instruction, and multiple instructions can be fetched at once using pipelining, thereby increasing efficiency.

True. Virtual memory combines the use of main memory and secondary storage (usually a hard disk) to provide a larger address space for a program. This allows the execution of programs that are larger than the available physical memory, by swapping parts of the program between main memory and secondary storage.