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Noida Institute of Engineering and Technology, GR. Noida (An Autonomous Institute) School of Computer Science & Engineering in Emerging Technologies Computer Basics Unit: 2 Logic Desig...

Noida Institute of Engineering and Technology, GR. Noida (An Autonomous Institute) School of Computer Science & Engineering in Emerging Technologies Computer Basics Unit: 2 Logic Design & Computer Ms. Swarnima Architecture (ACSAI0302) Assiatant Professor B Tech (AIML)- 3rd Sem Professor NIET, Greater Noida Swarnima Logic Design & Computer Architecture Unit 1 1 11/5/2024  BUS BUS A bus is a common pathway through which information flows from one computer component to another. It is a subsystem that is used to transfer data and other information between devices. Means various devices in computer like(Memory, CPU, I/O and Other) are communicate with each other through buses. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 2  Bus Architecture Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 3  System Bus A system bus is a single computer bus that connects the major components of a computer system, combining the functions of a data bus to carry information, an address bus to determine where it should be sent or read from, and a control bus to determine its operation. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 4  System Bus Types of Computer BUS: 1. Data Bus 2. Address Bus 3. Control Bus Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 5  System Bus 1. Data bus It is a bidirectional pathway that carries the actual data (information) to and from the main memory. Data Lines provide a path for moving data between system modules. It is bidirectional which means data lines are used to transfer data in both directions. CPU can read data on these lines from memory as well as send data out of these lines to a memory location or to a port. The no. of lines in data lines are either 8,16,32 or more depending on architecture. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 6  System Bus 2. Address bus Address Lines are collectively called as address bus. It is a unidirectional pathway that allows information to travel in only one direction. No. of lines in address are usually 16,20,24, or more depending on type and architecture of bus It is an internal channel from CPU to Memory across which the address of data(not data) are transmitted. It is used to identify the source or destination of data. Here the communication is one way that is, the address is send from CPU to Memory and I/O Port but not Memory and I/O port send address to CPU on that line and hence these lines are unidirectional. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 7  System Bus 3. Control bus It carries the control and timing signals needed to coordinate the activities of the entire computer. They are used by CPUs for Communicating with other devices within the computer. They are bidirectional. Typical Control Lines signals are Memory Read Memory Write I/O Read I/O Write ,etc Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 8  Bus Structure 1. Single Bus Structure – All units are connected to the same bus. 2. Multiple Bus Structure a) Traditional Configuration Uses three buses – local bus, system bus and expanded bus. a) High Speed BUS Configuration Uses high speed bus along with three buses – local bus, system bus and expanded bus used in traditional configuration. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 9  Single Bus Structure Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 10  Traditional Bus Configuration Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 11  Traditional Bus Configuration The traditional bus connection uses three buses local bus , system bus and expansion bus 1. Local bus connects the processor to cache memory and may support one or more local devices. 2. The cache memory controller connects the cache to local bus and to the system bus. 3. System bus also connects main memory module. 4. Input /output transfer to and from the main memory across the system bus do not interface with the processor activity because process accesses cache memory. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 12  Traditional Bus Configuration An expansion bus interface buffers data transfers between the bus and the I/O controllers on the expansion bus. Some typical I/O devices that might be attached to the expansion bus include Network cards (LAN) SCSI (Small Computer System Interface) Modem Serial Com Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 13  Traditional Bus Configuration Advantages of Traditional Bus Architecture A separate cache structure insulates the processor from the requirement to access the main memory frequently. This arrangement allows the system to support a wide variety of I/O devices and, at the same time, insulate memory to processor traffic from I/O traffic. Disadvantages of Traditional Bus Architecture The traditional bus architecture is reasonably efficient but begins to break down as higher, and higher performance is seen in the I/O devices. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 14  High Speed Bus Configuration Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 15  High Speed Bus Configuration There is a local bus that connects the processor to a cache controller, which is, in turn, connected to a system bus that supports the main memory. The cache controller is integrated into a bridge or buffering device that connects to a high-speed bus. This (High Speed) bus supports connections to high-speed LANs, such as Fast Ethernet at 100 Mbps, video and graphics workstation controllers to local peripheral busses, including SCSI and Firewire. An expansion bus still supports lower-speed devices, with an interface buffering traffic between the expansion bus and the high-speed bus. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 16  High Speed Bus Configuration Advantages of High-Performance Bus Architecture The advantage of this arrangement is that the high-speed bus brings high- demand devices into closer integration with the processor and, at the same time, is independent of the processor. So changes in processor architecture also do not affect the high-speed bus. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 17  Recap Bus Type Description A unidirectional pathway – information can only flow Address bus one way A bi-directional pathway – information can flow in two Data bus directions Carries the control and timing signals needed to Control bus coordinate the activities of the entire computer 11/5/2024 18 Swarnima Logic Design & Computer Architecture Unit 1  Bus Arbitration Bus Arbitration It refers to the process by which the current bus master accesses and then leaves the control of the bus and passes it to the another bus requesting processor unit. Bus master :The controller that has access to a bus at an instance. Bus Arbiter: It decides who would become current bus master. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 19  Bus Arbitration There are two approaches to bus arbitration: 1. Centralized bus arbitration A single bus arbiter performs the required arbitration and it can be either a processor or a separate DMA controller. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 20  Bus Arbitration 2. Distributed bus arbitration All devices participate in the selection of the next bus master. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 21  Bus Arbitration Methods of BUS Arbitration There are three arbitration schemes which run on centralized arbitration. 1. Daisy Chaining method 2. Polling method 3. Independent Request method Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 22  Daisy Chaining method Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 23  Daisy Chaining method Advantages – 1. Simplicity and Scalability. 2. The user can add more devices anywhere along the chain Disadvantages – 1. The value of priority assigned to a device is depends on the position of master bus. 2. Propagation delay is arises in this method. 3. If one device fails then entire system will stop working. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 24  Polling or Rotating Priority Method Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 25  Polling or Rotating Priority Method Advantages – 1. This method does not favor any particular device and processor. 2. The method is also quite simple. 3. If one device fails then entire system will not stop working. Disadvantages – 1. Adding bus masters is difficult as increases the number of address lines of the circuit. 11/5/2024 Swarnima Logic Design & Computer Architecture Unit 1 26  Fixed priority or Independent Request method Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 27  Fixed priority or Independent Request method Advantages – This method generates fast response. Disadvantages – Hardware cost is high as large no. of control lines are required. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 28  Recap Bus arbitration refers to the process by which the current bus master accesses and then leaves the control of the bus and passes it to the another bus requesting processor unit. There are two approaches to bus arbitration: Centralized and Distributed There are three arbitration schemes which run on centralized arbitration – Daisy chain, Polling and Independent request 11/5/2024 Swarnima Logic Design & Computer Architecture Unit 1 29  Register, bus and memory transfer Register They are used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. They are used to hold the temporary data. There are various types of Registers those are used for various purpose. Register Numbe Register Register Function Symbol r of bits Name DR 16 Data register Holds memory operands AR 12 Address register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction register Holds instruction code PC 12 Program counter Holds address of instruction TR 16 Temporary register Holds temporary data INPR 8 Input register Holds input character OUTR 8 Output register Holds output character Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 30  Register, bus and memory transfer Register Computer registers are designated by capital letters (sometimes followed by numerals) to denote the function of the register. The register that holds an address for the memory unit is memory address register and is designated by the name MAR. The program counter register is called PC, IR is the instruction register and R1 is a processor register Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 31  Register, bus and memory transfer Register Transfer Information transfer from one register to another is designated in symbolic form by means of a replacement operator. R2 R1 It denotes a transfer of the content of register R1 into register R2. It designates a replacement of the content of R2 by the content of R1 without changing the content of R1 after transfer. If the Register transfer is to occur only under a predetermined control condition, this can be shown by means of an if-then statement. If (P = 1) then (R2 R1) P: R2 R1, where P is a control function that can be either 0 or 1 Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 32  Register, bus and memory transfer Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 33  Register, bus and memory transfer Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 34  Register, bus and memory transfer Bus transfer A bus structure consists of a set of common lines, one for each bit of a register. Control signals determine which register is selected by the bus during each transfer. Multiplexers can be used to construct a common bus. Multiplexers select the source register whose binary information is then placed on the bus. The select lines are connected to the selection inputs of the multiplexers and choose the bits of one register Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 35  Register, bus and memory transfer Bus system for 4 registers Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 36  Register, bus and memory transfer Functional table for bus S1 S0 REGISTER SELECTED 0 0 A 0 1 B 1 0 C 1 1 D Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 37  Register, bus and memory transfer In general, a bus system will multiplex k registers of n bits each to produce an n- line common bus. This requires n multiplexers – one for each bit The size of each multiplexer must be k x 1 Transfer of information from the bus to one of many destination registers can be accomplished by connecting bus lines to the inputs of all designation registers and activating the load control of particular destination register selected. Symbolic statement- BUS C, R1 BUS, If bus is known to exist in the system, R1 C Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 38  Bus Transfer using Three state buffer Instead of using multiplexers, three-state gates can be used to construct the bus system A three-state gate is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 The third state is a high-impedance state – this behaves like an open circuit, which means the output is disconnected and does not have a logic significance. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 39  Bus Transfer using Three state buffer The three-state buffer gate has a normal input and a control input which determines the output state. With control 1, the output equals the normal input With control 0, the gate goes to a high-impedance state This enables a large number of three-state gate outputs to be connected with wires to form a common bus line without endangering loading effects Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 40  Bus Transfer using Three state buffer Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 41  Bus Transfer using Three state buffer Decoders are used to ensure that no more than one control input is active at any given time This circuit can replace the multiplexer. To construct a common bus for four registers of n bits each using three-state buffers, we need n circuits with four buffers in each Only one decoder is necessary to select between the four registers Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 42  Memory Transfer Most of the standard notations used for specifying operations on memory transfer are stated below. The transfer of information from a memory unit to the user end is called a Read operation. A memory word is designated by the letter M. We must specify the address of memory word while writing the memory transfer operations. The address register is designated by AR and the data register by DR. Thus, a read operation can be stated as: Read: DR ← M [AR] The Read statement causes a transfer of information into the data register (DR) from the memory word (M) selected by the address register (AR). Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 43  Memory Transfer The transfer of new information to be stored in the memory is called a Write operation. The Write statement causes a transfer of information from register R1 into the memory word (M) selected by address register (AR). Write: M [AR] ← R1 Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 44  Memory Transfer Memory Transfer Block diagram Above Diagram showing connections to memory unit. Write: M[AR] ← DR Read: DR ← M[AR] Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 45  Recap Registers are used to quickly accept, store, and transfer data and instructions that are being used immediately by the CPU. Multiplexers can be used to construct a common bus. A three-state gate is a digital circuit that exhibits three states – 0,1 and high impedance state. The transfer of information from a memory unit to the user end is called a Read operation. The transfer of new information to be stored in the memory is called a Write operation. 11/5/2024 Swarnima Logic Design & Computer Architecture Unit 1 46  Registers Registers are used to store data temporarily. Registers User Visible Register Control & Status Register 1. General Purpose Register 1. Program counter 2. Data Register 2. Instruction register 3. Address Register 3. MAR 4. Condition codes 4. MDR Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 47  Processor organization Processor organization means how the components of processor are connected and accomplish their task. Swarnima Logic Design & Computer Architecture Unit 1 11/5/2024 48  Processor organization-General register organization Most computers fall into one of three types of CPU organizations: Single accumulator organization. General register organization. Stack organization. 1. Single accumulator organization The instruction format in this type of computer uses one address field. All operations are performed with an implied accumulator register. Example : ADD X where X is the address of the operand. The ADD instruction in this case results in the operation AC