Types of Memory.pdf

Types of Memory random access memory (RAM). read-onlymemory (ROM). Dynamic RAM (DRAM) consists of capacitors that slowly leak their charge over time. must be refreshed every few milliseconds to prevent data loss. “cheap” memory owing to its simple design. Static RAM (SRAM). consists of circuits simi...

Types of Memory random access memory (RAM). read-onlymemory (ROM). Dynamic RAM (DRAM) consists of capacitors that slowly leak their charge over time. must be refreshed every few milliseconds to prevent data loss. “cheap” memory owing to its simple design. Static RAM (SRAM). consists of circuits similar to the D flip-flop very fast memory, doesn’t need to be refreshed like DRAM does. It is used to build cache memory, does not need to be refreshed, it needs very little charge to retain its memory. store permanent, or semi-permanent data even the system is turned off. The Memory Hierarchy To provide the best performance at the lowest cost, memory is organized in a hierarchical fashion. Small, fast storage elements are kept in the CPU, o larger, slower main memory is accessed through the data bus. o Larger, permanent storage in the form of disk and tape drives is still further from the CPU. To access a particular data, o the CPU first sends a request to its nearest memory = cache. o If the data is not in cache, then main memory is queried. o If the data is not in main memory, then the request goes to disk. o When data is located → data + no. nearby data elements = fetched into cache memory. Definitions Hit Miss when data is found at a given memory level. An entire block of data is copied after a hit because the principle of locality = o once a byte is accessed, the nearby data element will be needed when it is not found. Hit Rate the percentage of time data is found at a given memory level. Miss Rate the percentage of time it is not. Miss rate = 1 – hit rate. Hit Time the time required to access data at a given memory level. Miss Penalty the time required to process a miss, including the time that it takes to replace a block of memory plus, the time it takes to deliver the data to the processor. Forms Of Locality Temporal locality: Recently-accessed data elements tend to be accessed again. Spatial locality: Accesses tend to cluster. Sequential locality: Instructions tend to be accessed sequentially. Cache Memory speed up accesses by storing recently used data closer to the CPU, instead of storing it in main memory. smaller than main memory, access time is a fraction of that of main memory. The simplest cache mapping scheme is direct mapped cache. In a direct mapped cache consisting of o N (10) blocks of cache, o block X (7) of main memory maps to cache block Y = X mod 10. (7, 17, 27, 37) Perform direct mapping, the binary main memory address is partitioned into o The offset field uniquely identifies an address within a specific block. o The block field selects a unique block of cache. o The tag field is whatever is left over. o The sizes of these fields are determined by characteristics of both memory and cache. Placing memory blocks in specific cache locations based on memory address Example: Consider a byte-addressable main memory consisting of 4 blocks, and a cache with 2 blocks, where each block is 4 bytes = 8 memory to 4 catch In summary, direct mapped cache maps main memory blocks to cache blocks. The mapping depends on: No. bits in the main memory address (how many addresses exist in main memory). No. blocks are in cache (which determines the size of the block field). How many addresses (bytes or words) are in a block (size of the offset field)? fully associative cache: placing memory blocks anywhere in cache would have to fill up before any blocks are evicted. A memory address is partitioned into only two fields: the tag and the offset. When the cache is searched, all tags are searched in parallel to retrieve the data quickly. This requires special, costly hardware. Suppose, as before, we have 14-bit memory addresses and a cache with 16 blocks, each block of size 8. direct mapped cache evicts a block whenever another memory reference needs that block. The block that is evicted is the victim block. fully associative cache no mapping, must devise an algorithm to determine which block to evict from the cache. Set associative cache combines direct mapped cache + fully associative cache. N-way set associative cache mapping o like direct mapped cache o memory reference maps to particular location in cache. Unlike direct mapped cache, a memory reference maps o to a set of several cache blocks, similar to the way in which fully associative cache works. o can map only to the subset of cache slots. fully associative and set associative cache, replacement policy is invoked when it becomes necessary to evict a block from cache. depends upon the locality that we are trying to optimize we are interested in temporal locality. optimal replacement policy look future to see which blocks won’t be needed for the longest period of time. optimal replacement algorithm impossible to implement a benchmark for assessing the efficiency of any other scheme we come up with. least recently used (LRU) algorithm keeps track of the last time that a block was assessed evicts the block that has been unused for the longest period of time. The disadvantage of this approach is its complexity: has to maintain an access history for each block, which ultimately slows down the cache. First-in, first-out (FIFO) is a popular cache replacement policy. the block that has been in the cache the longest, regardless of when it was last used. A random replacement policy: o It picks a block at random and replaces it with a new block. o evict a block that will be needed often or needed soon, but it never thrashes. effective access time (EAT). Measure the performance of hierarchical memory weighted average: hit ratio and relative access times of successive levels of memory. two-level memory = EAT = H x AccessC + (1 – H) x AccessMM o H = cache hit rate, o AccessC = access times for cache o AccessMM = access times for main memory. For example, consider a system with a main memory access time of 200ns supported by a cache having a 10ns access time and a hit rate of 99%. Suppose access to cache and main memory occurs concurrently (the accesses overlap). The EAT is: 0.99(10ns) + 0.01(200ns) = 9.9ns + 2ns = 11ns improve cache performance victim cache: adding a small associative cache to hold blocks that have been evicted recently. trace cache: variant of an instruction cache - holds decoded instructions for program branches, giving the illusion that noncontiguous instructions are really contiguous. multilevel cache hierarchies: The levels of cache form their own small memory hierarchy. Level 1 cache (8KB to 64KB) is situated on the processor itself Access time = 4ns. Level 2 cache (64KB to 2MB) may be on the motherboard, expansion card. Access time = 15–20ns. inclusive cache, the same data may be present at multiple levels of cache. Strictly inclusive caches guarantee that all data in a smaller cache also exists at the next higher level. Exclusive caches permit only one copy of the data. The tradeoffs in choosing one over the other involve o weighing the variables of access time, o memory size, o circuit complexity.