SYSMOD_CH3.pdf

System Level Modeling AMS Languages Lecture for the 3rd semester - SS 2024 – CH3 Guillermo Conde Engineering & IT, ISCD (master) Pictures © of individual owners as mentioned as reference. To be used for educationa...

System Level Modeling AMS Languages Lecture for the 3rd semester - SS 2024 – CH3 Guillermo Conde Engineering & IT, ISCD (master) Pictures © of individual owners as mentioned as reference. To be used for educational purposes within ISCD curriculum. May change w/o notice, use at your own risk. Everything else © CUAS. AMS – hardware description languages System level: SystemC-AMS Many different models of computation, script based (algorithmic) approaches or M, Python, C/C++ proprietary tools/languages (Modelica, Simulink) Digital domain: Discrete event solver as part of model (RNM), SystemVerilog HDL allows behav. descriptions, (logic gate) netlists VHDL Analogue domain: ODE solver, Verilog-A HDL defines equation systems (not only electrical) VHDL-AMS Device level: netlist with primitive elements, SPICE no HDL in this sense (only macro modeling) WWW.FH-KAERNTEN.AT VHDL-AMS history VHDL was initiated in 1981 by the United States Department of Defence (DoD) to develop a language to be used throughout technology and design methodology This led to the IEEE 1076 standard DoD Mil Std 454 became mandatory, requiring a VHDL description for any ASIC VHDL-AMS is an extension of IEEE 1076-1993 to allow description of ordinary and algebraic equations The VHDL-AMS was finalized as IEEE 1076.1-1999 Dr. Kenneth Bakalar is one of the principal language architects of this standard WWW.FH-KAERNTEN.AT anatomy of a VHDL program VHDL describes event-based models A change in a signal creates an event The events are timely sorted and passed to the corresponding processes These processes change signals and create new events library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binary_4_bit_adder_top is Port ( NUM1 : in STD_LOGIC_VECTOR (3 downto 0) := "0000"; NUM2 : in STD_LOGIC_VECTOR (3 downto 0) := "0000"; SUM : out STD_LOGIC_VECTOR (3 downto 0) ); end entity binary_4_bit_adder_top; architecture behav of binary_4_bit_adder_top is begin sum : process (NUM1, NUM2) is begin SUM