CSD Practical Guide PDF

IMPORTANTS OF CSD PRACTICAL Practical 1 i. **[AND Gate: (IC7408)(kit/logisum)]** The AND gate produces a HIGH output when all of the inputs are HIGH. When any inputs are LOW, the output is LOW.\ The standard symbol for an AND gate is shown in figure below along withthe associated Truth Table ht...

IMPORTANTS OF CSD PRACTICAL Practical 1 i. **[AND Gate: (IC7408)(kit/logisum)]** The AND gate produces a HIGH output when all of the inputs are HIGH. When any inputs are LOW, the output is LOW.\ The standard symbol for an AND gate is shown in figure below along withthe associated Truth Table http://www.care4you.in/Tutorials/DE%20Lab/images/exp-1/AND.png Pin Diagram:  ii. **THE OR GATE (IC7432)(kit/logism)** The OR gate produces a HIGH output when any or all of the inputs is HIGH. When both inputs are LOW, the output is LOW.\ The standard symbol for an OR gate is shown in figure below along with the Associated TruthTable.  http://www.care4you.in/Tutorials/DE%20Lab/images/exp-1/or.png Pin Diagram:  iii. **THE NOT GATE(IC7404)(kit/logism)** A NOT gate, often called an inverter, it has only a single **input**  and single output. A NOT gate performs logical negation on its **input**. In other words, if the **input** is HIGH, then the **output** will be LOW and vice versa. The standard symbol for an NOT gate is shown in figure below along with the associated Truth Table Image result for symbol of not gate  Pin Diagram: [iv) XOR gate 7486(kit / Logism)] - Definition The exclusive OR gate is a modified OR gate that produces a HIGH output when only one of the inputs is HIGH. When both inputs are HIGH or when both inputs are LOW, the output is LOW. The standard symbol for an XOR gate is shown in figure below along withthe associated Truth Table  - [Truth table ] [Pin Diagram:]  V\) NAND Gate: THE NAND GATE (IC7400) The NAND gate produces a LOW output when all of the inputs are HIGH. The abbreviation for this gate is NAND and is ANDGATE followed with NOT GATE. When any inputs are LOW, the output isHIGH. The standard symbol for an NAND gate is shown in figure below along with the associated Truth Table. - NAND to NOT gate(logism) - Definition Of NAND Gate: - [Logic diagram]  - [Truth table of NOT Gate] - NAND toAND gate(logism) NAND is the universal gate. We can design all basic gates through NAND gate - [Logic diagram]  - [Truth table] - NAND to OR gate(logism) Definition Of NAND Gate: - [Logic diagram ]  - [Truth table] Practical 2 - Demorgan theorems Or Law 1)Demorgan theorems 1(kit/Logism) - Definition According to the first theorem given by De Morgan, when two or more variables are AND and then complemented, it is equal to the OR of the complement of each variable individually. - [Diagram ]  - [Expression] - [Truth table] ------- ------- ---------- --------- Input Input Output Output A B F=(A.B)' F=A'+B' 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 ------- ------- ---------- --------- 2)Demorgan theorms 2 (kit/Logism) - Definition According to the second theorem given by De Morgan, when two or more variables are OR and then complemented, it is equal to the AND of the complement of each variable individually. - [Diagram]  - [Expression] [Truth table] ------- ------- ---------- --------- Input Input Output Output A B F=(A+B)' F=A'.B' 1 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 ------- ------- ---------- --------- 3. [Reduce the given Boolean expression] Q=AB+BC(B+C) - [Logical circuit of complex boolens]  - [Apply booleans law to the given expression] AB+BC(B+C) AB+BBC+BCC \[Distributing Term\] AB+BC+BC \[Applying Identity AA=A\] AB+BC \[Applying Identity B+B=B\] B(A+C) \[Factoring B Out Of Term\] Reduce Expression :B(A+C) - [Logical circuit of reduce boolean expression] - [Truth table] ------- ------- ------- --------------------------- -------------------------- Input Input Input Output of complex circuit Output of Reduce circuit A B C Q=AB+BC(B+C) Q=B(A+C) 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 ------- ------- ------- --------------------------- -------------------------- Practical 3 - Reduction of Boolean Expression by Karnaugh Map(K-map) For simplification of Boolean expression byKarnaugh map ,it is necessary to represent it in standard form. There are two standard Canonical Form :SOP(sum of product) & POS(product of sum) Each term of SOP is known as 'minterm' and it's output is 1. Each term of POS is known as 'maxterm' and it's output is 0. - Simplify the given sop expression F=AB'+A'B+AB - K map  - Reduce expression F=A+B - Logical circuit of complex expression - Logical circuit of reduce expression  Truth table ------- ------- --------------------------- -------------------------- Input Input Output of Complex circuit Output of Reduce circuit A B F=A'B+AB'+AB F=A+B 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 ------- ------- --------------------------- -------------------------- PRACTICAL 4 - Code converter 1)Binary to gray Logical expression for k map - Diagram  Truth table ---- ---- ---- ---- -- ---- ---- ---- ---- B4 B3 B2 B1 G4 G3 G2 G1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 ---- ---- ---- ---- -- ---- ---- ---- ---- 2)Gray to binary - From K map,we get  - Diagram - Truth table ---- ---- ---- ---- -- ---- ---- ---- ---- G4 G3 G2 G1 B4 B3 B2 B1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 ---- ---- ---- ---- -- ---- ---- ---- ---- Practical 5 - Adders and Subtractors 1)Half adder (logism /Kit) - Definition The half adder is an arithmetic circuit used to perform two single-bit addition. Theinput to the half adder is a two-bit data while the output comprises sum and carry outputs. For betterunderstanding purposes let us have a look at the block diagram of a half adder circuit where A and Bbe the two inputs, and S(sum) and C(carry) are the two outputs. - Logic diagram  - Truth table ------- ------- -------- -------- Input Input Output Output A B SUM CO 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 ------- ------- -------- -------- 2)Halfsubtractor(logisim) - Definition A halfsubtractor is another combinational circuitthat performs one-bitsubtractiontogenerate a difference. The block diagram of a half subtractor is shown below. There are two inputlines namely A and B, and two output lines namely difference(d) and borrow(b). - Logic diagram - Truth table ------- ------- ------------ -------- Input Input Output Output A B DIFFERENCE BORROW 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 ------- ------- ------------ -------- 3)Full adder(logisim) - Definition Similiar to half adder a full adder is also an arithmetic circuit, used to perform theaddition of three input bits. There are three input lines (assume A, B and, C) and two output lines namely sum and carry. - Logic diagram  - Truth table ------- ------- ------- -------- -------- Input Input Input Output Output A B C IN SUM CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ------- ------- ------- -------- -------- 4)Fullsubtractor (logism) - Definition The full subtractor as the name signifies performs the arithmetic subtraction ofthe three input data line and gives an output. The block diagram of a full subtractor is as below. Itcomprises three input lines A, B, and, C and two output lines d (difference) and b (borrow). - Logic diagram - Truth table ------- ------- ------- ------------ -------- Input Input Input Output Output A B BIN DIFFERENCE BOUT 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 ------- ------- ------- ------------ --------